Applications
MU9C8338A 10/100Mb Ethernet Filter Interface
Table 29: Add Permanent Entry Routine
Line
/CM
H
/W
L
/E Cycle
Short
Short
Short
Short
Long
/EC
H
Mnemonic
DQ(15:0)
Description
1
2
3
4
5
ddddH
ddddH
ddddH
ddddH
0334H
Write Perm Bit and Port ID to Segment 0
Write 1st 16 bits to Segment 1
Write 2nd 16 bits to Segment 2
Write 3rd 16 bits to Segment 3
Move to Next Free
H
L
H
H
L
H
H
L
H
L
L
H
MOV_NF,CR,V
Table 30: Delete Entry Routine
Line
/CM
H
/W
L
/E Cycle
Short
Short
Short
Short
Long
/EC
H
Mnemonic
DQ(15:0)
xxxxH
Description
1
2
3
4
5
Dummy Write to Segment 0
Write 1st 16 bits to Segment 1
Write 2nd 16 bits to Segment 2
Write 3rd 16 bits to Segment 3 and compare
Set Highest Match to “Empty”
H
L
H
ddddH
ddddH
ddddH
042DH
H
L
H
H
L
L
L
L
H
VBC_HM,E
Table 31: Set Address Register Routine
Line
/CM
L
/W
L
/E Cycle
Short
/EC
H
Mnemonic
SBR
DQ(15:0)
0619H
0220H
aaaaH
0618H
Description
1
2
3
4
Select Background Register set
Target Address register
Address value
L
L
Short
H
TCO_AR
L
L
Short
H
L
L
Short
H
SFR
Select Foreground Register set
Table 32: Read Entries Routine
Line
1
/CM
L
/W
L
/E Cycle
Short
Short
Short
Long
Long
Long
Long
Med
/EC
H
Mnemonic
SBR
DQ(15:0)
0619H
0228H
ppppH
ddddH
ddddH
ddddH
ddddH
ddddH
ddddH
0228H
FFFFH
0618H
Description
Select Background Register set
Target Device Select register
Page Address value
2
L
L
H
TCO_DS
3
L
L
H
4
H
H
H
H
L
H
H
H
H
H
H
L
H
Data Read, Segment 0
5
H
Data Read, Segment 1
6
H
Data Read, Segment 2
7
H
Data Read, Segment 3
8
H
Command Read, Status Register bits 15:0
Command Read, Status Register bits 31:16
Target Device Select register
Select all devices
9
L
Med
H
10
11
12
L
Short
Short
Short
H
TCO_DS
SFR
L
L
H
L
L
H
Select Foreground Register set
Rev. 0a
21
MUSIC [ MUSIC SEMICONDUCTORS ]
