MU9C8338A 10/100Mb Ethernet Filter Interface
Timing Diagrams
Table 37: REJ (Base 10) Timing Data
No.
36
37
38
39
40
Symbol
tJLRCH
tRCHJH
tJHJL
Parameter (ns)
Min
400
Max
Notes
REJ to rising edge of RX_CLK
Rising edge of RX_CLK to REJ (after SFD event)
REJ assertion width
4800
50400
2*RX_CLK
20
tRCHJH
tRCHSL
RX_CLK rising edge to REJ HIGH
RX_CLK rising edge to REJ LOW
0
0
20
39
40
RX_CLK
RXD[3:0]
RX_DV
/REJ
Preamble
SFD DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 SA0 SA1
36
37
38
Table 38: REJ (Base 100) Timing Data
No.
41
42
43
44
45
Symbol
tJLRCH
tRCHJH
tJHJL
Parameter (ns)
Min
40
Max
Notes
REJ to rising edge of RX_CLK
Rising edge of RX_CLK to REJ (after SFD event)
REJ assertion width
480
5040
2*RX_CLK
tRCHJH
tRHJL
RX_CLK rising edge to REJ HIGH
RX_CLK rising edge to REJ LOW
0
0
20
20
44
45
RX_CLK
RXD[3:0]
RX_DV
/REJ
Preamble
DA10
DA11 SA0 SA1
SFD DA0 DA1 DA2 DA3 DA4 DA5 DA6
DA7 DA8 DA9
41
42
43
Table 39: FRX_ER in Relation to REJ and RX_ER Timing Data
No.
46
47
48
49
Symbol
tJLFEH
Parameter (ns)
Min
0
Max
Notes
Delay REJ LOW to FRX_ER HIGH
Delay RX_ER HIGH to FRX_ER HIGH
Delay REJ HIGH to FRX_ER LOW
Delay RX_ER LOW to RX_ER LOW
SYSCLK+RX_CLK+10
tREHFEH
tJHFEL
0
20
0
SYSCLK+RX_CLK+10
20
tRFLFEL
0
48
46
47
/REJ
49
RX_ER
FRX_ER
26
Rev. 0a
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