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MU9C8338 参数 Datasheet PDF下载

MU9C8338图片预览
型号: MU9C8338
PDF下载: 下载PDF文件 查看货源
内容描述: 10 / 100Mb的以太网接口筛选 [10/ 100Mb Ethernet Filter Interface]
分类和应用: 以太网
文件页数/大小: 28 页 / 428 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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MU9C8338 10/100Mb Ethernet Filter Interface  
Software Model  
SOFTWARE MODEL  
System Registers  
One set of registers is available to address the MU9C8338  
component and its attached LANCAMs as a single system.  
The application decodes one range of addresses to produce  
a Processor Chip Select System signal (/PCSS). The  
lowest address in this application-defined address range,  
shown in Table 3, is referred to as SYSTEM_BASE.  
Table 3: System Registers  
Name  
R/W  
R
Description  
Address  
Default Settings  
N/A  
SSTAT  
System Status  
SYSTEM_BASE + 0H  
SYSTEM_BASE + 1H  
SYSTEM_BASE + 2H  
SYSTEM_BASE + 3H  
SYSTEM_BASE + 5H  
SYSTEM_BASE + 6H  
SYSTEM_BASE + 7H  
SYSTEM_BASE + 8H  
SYSTEM_BASE + 9H  
SYSTEM_BASE + AH  
SYSTEM_BASE + CH  
SYSTEM_BASE + DH  
SYSTEM_BASE + EH  
SYSTEM_BASE + 10H  
SYSTEM_BASE + 11H  
SYSTEM_BASE + 12H  
SYSTEM_BASE + 20H  
SYSTEM_BASE + 21H  
SYSTEM_BASE + 24H  
SYSTEM_BASE + 26H  
SYSTEM_BASE + 27H  
SYSTEM_BASE + 28H  
SYSTEM_BASE + 29H  
SSCFG  
W
System Static Configuration  
System Dynamic Configuration  
System Targets  
0000H  
0H  
SDCFG  
W
STARG  
W
0H  
SCDW0  
R/W  
R/W  
R/W  
R/W  
R
CAM Data Word 0  
N/A  
SCDW1  
CAM Data Word 1  
N/A  
SCDW2  
CAM Data Word 2  
N/A  
SCDW3  
CAM Data Word 3  
N/A  
STPURG  
STCURR  
SMXSADACYC  
SCSWB  
Time Stamp to Purge  
01H  
R
Time Stamp Current  
00H  
W
Max SA/DA Cycle  
20H  
R
CAM Status Word B  
N/A  
SCSWA  
R
CAM Status Word A  
N/A  
SSAU  
W
SA Update Op-Code  
0368H  
0334H  
0FH  
SSAL  
W
SA Learn Op-Code  
SLCCS  
W
LANCAM Control Signals  
Perform Delete Sequence  
Perform Add Sequence  
Perform Read Sequence  
Perform Increment STCURR Sequence  
Perform Increment STPURG Sequence  
Perform Increment STCURR & STPURG Sequence  
Perform SetAddr. Sequence  
SDO_DELETE  
SDO_ADD  
SDO_READ  
SDO_INCTS  
SDO_INCPR  
SDO_INCTSPR  
SDO_SETADD  
W
N/A  
W
N/A  
W
N/A  
W
N/A  
W
N/A  
W
N/A  
W
N/A  
System Status Register  
Table 5 shows a CAM_SPD setting for a 120 ns speed  
grade LANCAM component. 120 ns LANCAMs are no  
longer available and it is recommended that when using a  
90 ns LANCAM, set SSCFG[3:1] to 000. This setting  
accommodates most applications and has the added  
benefit of using the least amount of power.  
The System Status register (SSTAT) provides a CPU  
visibility into the state of the LANCAM array. The /FF bit  
indicates the current state of the Full Flag output of the  
LANCAM array. The /MF bit indicates the Match Flag  
output of the LANCAM array.  
Table 5: SSCFG: System Static Configuration  
Register  
Table 4: SSTAT: System Status Register Mapping  
Name  
/FF  
Bits  
0
Description  
Name  
Bits  
Description  
Full Flag from LANCAM array  
Match Flag from LANCAM array  
CAM_SPD  
3:1  
000 = 120 ns (90 ns)  
001 = 90 ns  
/MF  
1
010 = 70 ns  
System Static Configuration Register  
011 = RESERVED  
100 = RESERVED  
101 = RESERVED  
110 = RESERVED  
111 = RESERVED  
The System Static Configuration register (SSCFG) allows  
the CPU to configure the LANCAM array. These are set  
and forget values. The CAM_SPD sets the controller to  
match the speed grade of the LANCAM components  
attached. A 50MHz clock is assumed. The INV_REJ bit  
configures the REJ port to be active LOW instead of active  
HIGH.  
INV_REJ  
0
0 = Active HIGH  
1 = Active LOW  
12  
Rev. 1a  
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