MU9C8338 10/100Mb Ethernet Filter Interface
Functional Description
Destination Address Processing
2. External circuitry can monitor the status of the
Result Port Data valid (RP_DV) output pin. This
output indicates that there is a result available in the
internal register which can be read through the Result
port. The external circuitry can read the data by
asserting the Result Port Select (RP_SEL) pin.
Assertion of Result Port Next (RP_NXT) clears the
value and advances the next entry if there is one
available.
Once configured, the MU9C8338 will extract the DA from
the frames that are received through the MII port. An
automatic address processing function is subsequently
triggered. Once the DA processing function is triggered,
the frame is monitored to detect whether it is a broadcast,
multicast, or unicast frame and the appropriate actions are
taken. DA processing consists of the following actions:
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Packets are characterized as Broadcast, Multicast, or
Unicast types.
Source Address Processing
Once configured, the MU9C8338 also will perform SA
processing functions after the address information has
been extracted from a received frame. The SA of each
arriving frame is stored by the MU9C8338 for further
processing, along with the port ID and the current time
stamp. Note that at start-up, permanent addresses and their
Port ID are loaded into the LANCAM through the CPU
port; as message traffic proceeds, new addresses are
learned and added to the LANCAM database, and aged
addresses are purged. SA processing consists of the
following actions:
Unicast packets initiate a search of the CAM for
existing entries.
If a DA match is found, the Port ID read from the
CAM is compared to the Source Port ID. If the Source
Port ID and Destination Port ID match, the frame is
rejected. If the Port IDs are different, the Tag
information is made available for MACs that support
Tag switching, through the Tag port.
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If the MU9C8338 rejects the frame, it asserts the
Reject output pin (REJ) and forces the MII RX_ER
output (FRX_ER) HIGH for the MII Port. This causes
the MAC to discard the frame.
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The SA field is collected and temporarily stored. Note
the SA cannot be a Broadcast or Multicast address by
definition.
Once the DA processing function is complete, the
MU9C8338 stores the result. This result indicates the
characterization of the processed frame. (Broadcast,
Multicast, or Unicast) and the Source Port ID.
Additionally, if a unicast frame was processed, the
result of the search and the port ID of the DA is also
stored. Finally, the detail of whether the Destination
port and the Source port are identical is also stored.
When the complete packet has arrived, the CRC field
is checked and the length of the packet is checked.
Any errors result in no further SA processing.
If the packet did not contain any errors, (or the CRC
check facility is disabled), the SA field is compared
with the address fields that are stored in the
LANCAM.
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The result of DA processing may be read in two ways.
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If a match is found, the Port ID and time stamp for
that entry are updated. If no match is found, the SA is
added to the CAM, along with the current time stamp
and the Port ID assigned to that particular Source port.
1. An interrupt may be sent to the host processor
indicating that there is a result available. The host
processor would read the result from an internal
Result Data register.
Functional Blocks
The building blocks that make up the MU9C8338 are
shown in Figure 3, and their functions are described by the
following.
the RX_ER pin, is forced to HIGH at the same time. If the
DA is matched in the LANCAM, the TP_DV pin is
asserted and the destination port ID, high-order bit first, is
clocked out through the TP_SD pin transitioning after the
RX_CLK rising edge.
MII Interface (MII Port)
The incoming asynchronous receive data is registered for
subsequent processing. MU9C8338 internal processing is
synchronous with the system clock.
MAC Receiver
This block performs tasks that are a subset of the Ethernet
MAC. It detects errors, (CRS, COL, RX_ER, and Runt
Frame), determines the start of frame, parses addresses,
computes the CRC for 10Base-X packets, and formats the
4-bit nibbles into 48-bit SA and DA registers.
Tag Port Interface (Tag Port)
Rejection of a packet is indicated by the assertion of REJ.
The FRX_ER line, which otherwise reflects the state of
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Rev. 1a
MUSIC [ MUSIC SEMICONDUCTORS ]
