MU9C8338 10/100Mb Ethernet Filter Interface
Software Model
Port Registers
The MU9C8338 supports one port. This port is addressed
as an offset to the CHIP_BASE for the MU9C8338 in
which it is implemented. Table 21 shows the Port registers
and their address values.
Table 21: Port Registers
Name
PID
R/W
W
Description
Port ID
Address
Default
0H
CHIP_BASE + 40H
CHIP_BASE + 41H
CHIP_BASE + 42H
PCFG
PTARG
W
Configure Port
Target Port
0H
W
0H
Port ID Register
Port Target Register
The Port ID register stores the ID associated with the MII
port. The 6-bit value is the value added to LANCAM
entries when the SA search routine is performed.
The Port Target register allows the operating conditions of
the port to be set. Bits 3:0 are Reserved and should be set
to 0H. Bits 5 and 4 determine what action is taken after the
DA is extracted from a frame that was received on the MII
port. Bits 7 and 6 determine what action is taken after the
SA is extracted from a frame that was received on the MII
port.
Table 22: PID: Port ID Register Mapping
Name
Bits
Description
PORT_ID
5:0
6-Bit Port ID
Table 24: PTARG: Port Target Register Mapping
Port Configure Register
Name
Bits Description
The Port Configure register enables or disables the
10Base-X CRC check facility. If the facility is enabled,
10Base-X packets found to have CRC errors will not have
their Source address processed. If the facility is disabled,
the Source address of 10Base-X packets are processed
regardless of CRC errors, assuming the PTARG register is
configured appropriately.
SA
7:6
5:4
00: SAs are ignored
01: SAs are processed
10: RESERVED
11: RESERVED
DA
00: DAs are ignored
01: DAs are processed
10: DAs are processed and trigger a
CPU interrupt
This register only enables a CRC check for 10Base-X
packets. The facility should be disabled (bit 1=0) for
100Base - X packets.
11: RESERVED
RESERVED
3:0
Must be set to 0H.
All other values: RESERVED
Table 23: PCFG: Port Configure Register Mapping
Name
Bits
0
Description
RESERVED
Enable CRC Check
Write 0
1
0 = Disable (default)
1 = Enable
16
Rev. 1a
MUSIC [ MUSIC SEMICONDUCTORS ]
