Software Model
MU9C8338 10/100Mb Ethernet Filter Interface
The System Dynamic Configuration Register
System CAM Word Registers
The System Dynamic Configuration Register (SDCFG)
allows the CPU to control the MU9C8338 /RESET_LC
output pin. This pin normally would be connected to the
/RESET input of all the LANCAMs in a chain of
LANCAMs. When the RST_CAM bit is logic 0 the
/RESET_LC output is LOW and when the RST_CAM bit
is logic 1 the /RESET_LC output is HIGH. Note that if a
hardware reset is performed by taking the MU9C8338
/RESET input LOW, /RESET_LC is asserted LOW.
However once /RESET has been taken HIGH,
/RESET_LC remains LOW, holding the LANCAM(s) in
the reset condition. The RST_CAM bit must be set to 1 to
return /RESET_LC HIGH and hence allow the
LANCAMs to operate normally.
When using the series of built-in routines, the SCDW
registers are used to transfer data. The bit mapping is
different for each routine. Please refer to the appropriate
mapping for the relevant routine. Also refer to section
MAC Address Storage on page 9.
Table 8: SCDW: Data Mapping
Contents
Name
SDO_DELETE
Sequence
Other Routines
SCDW0 [15:0]
SCDW1 [15:0]
SCDW2 [15:0]
SCDW3 [15:0]
MAC_AD [15:0]
MAC_AD [31:16]
MAC_AD [47:32]
Not used
Associated data
MAC_AD [15:0]
MAC_AD [31:16]
MAC_AD [47:32]
Table 6: SDCFG System Dynamic Configuration
Register
During the LANCAM initialization and configuration
process, SCDW0 is used with SLCSS to configure the
LANCAMs. When SCDW0 is used to transfer associated
data, the bit mapping is as shown in Table 9.
Name
Bits
Description
RST_CAM
0
0: Reset
1: Normal Operation
SCDW0 has an additional purpose that allows the
associated data to be read after a DA processing function
has completed. After every DA is processed, the
associated data read from the LANCAM is placed in the
SCDW0 register, Therefore, if the system software reads
the SCDW0 register after a packet is processed, the Port
ID, Timestamp, and permanent bit information may be
found.
System Target Register
The System Target Register (STARG) allows the CPU to
determine how events are to be handled. The INCR_PIN
bits enable or disable to INCR hardware input. The
EN_FF_INT bits enable or disable whether the LANCAM
/FF output will produce an interrupt when the LANCAM
is full.
Table 7: STARG: System Target Register Mapping
Table 9: SCDW0: Associated Data Register
Mapping
Name
Bits
Description
INCR_PIN
3:2
00: Disable INCR pin
01: RESERVED
10: RESERVED
Name
Bits
7:0
13:8
14
Time_Stamp
Port_ID
11: Enable INCR pin
EN_FF_INT
1:0
00: Disable /FI interrupt
01: RESERVED
10: Enable /FI interrupt
11: RESERVED
Reserved
Permanent
15
System Time Stamp Purge Register
The System Time Stamp Purge register (STPURG) stores
the purge time stamp value. It is a read-only register, but it
may be incremented by writing an arbitrary value to the
SDO_INCPR register.
Table 10: STPURG: System Time Stamp Purge
Register Mapping
Name
Location
Purge Time Stamp Initial Value=01H
bits [7:0]
Rev. 1a
13
MUSIC [ MUSIC SEMICONDUCTORS ]
