MU9C8328A Ethernet Interface
APPLICATIONS Continued
the Persistent destination to the Comparand register as
shown in Table 3. If only one LANCAM is used, Table 3
would be modified to replace steps 9 through 14 with a
TCO DS (0228H) followed by a 0000H.
Responding to Interrupts
Depending on the filtering or error interrupt conditions set
in the MU9C8328A Control register, the /INT line will assert
at the end of the frame SA field. The host can then read the
MU9C8328A Status register to determine the cause of the
interrupt, whereupon the Status register is reset. If there
was a DA match interrupt and read associated data was
set, then the associated data segment stored in the
LANCAM at the same location that matched the frame’s
DA can be read out of the Associated Data register (03H).
Enabling Network Activity
After the LANCAMs have been initialized, the MU9C8328A
is enabled to begin processing network traffic by setting
bit 13 (NETEN) in its Control register to a 1 along with the
desired filtering actions and interrupt enables.
Step A(2–0) /WE Mnemonic D(15–0) Comments
1
2
3
4
5
6
7
8
0H
5H
5H
5H
5H
5H
5H
5H
5H
5H
5H
5H
5H
5H
5H
5H
5H
5H
5H
5H
7H
5H
5H
5H
5H
5H
5H
5H
7H
7H
7H
7H
5H
5H
5H
5H
0H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
C000H Pass all frames during initialization
0000H Command Read to reset LANCAM state machines
0228H Selects all Device Select registers
FFFFH Selects all LANCAMs
TCO_DS
TCO_CT
TCO_PA
0200H Selects all Control registers
0000H Resets all memory locations
0208H Selects first Page Address register
0000H Writes first Page Address value
0700H Sets Full flag on first LANCAM
0208H Selects second Page Address register
0001H Writes second Page Address value
0700H Sets Full flag on second LANCAM
0200H Selects all Control registers
0000H Resets all Full flags
SFF
TCO_PA
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
SFF
TCO_CT
SBR
TCO_CT
0619H Select Background Register set
0200H TCO CT
8111H
48RAM, 16CAM, MR1, Enhanced mode
TCO_SC
0210H Select Segment Control register
0000H Set Read and Write to segment 0
0108H Set Persistent Destination to Mask Register 1
FFF0H Setup Time Stamp in lowest 8 bits of segment 0
0100H Set Persistent Destination to Comparand register
0618H Select Foreground Register set
SPD_MR1
SPD_CR
SFR
TCO_CT
0200H Select Command register
8041H 48CAM, 16RAM, No Mask, Enhanced mode
0108H Set Persistent Destination to Mask Register 1
0210H Select Segment Control register
1C04H Set to write Segments 0, 1, 2, and 3
FFF0H Write to Segment 0 of MR1
FFFFH Write to Segment 1 of MR1
FFFFH Write to Segment 2 of MR1
FFFFH Write to Segment 3 of MR1
0100H Set Persistent Destination to Comparand register
0210H Select Segment Control register
SPD_MR1
TCO_SC
SPD_CR
TCO_SC
3808H Write Segments 1–3, Read Segment 0
0005H Set Persistent source to Highest match
290BH Enable filter, Negative filter on DA, enable learn
SPS_HM
Table 3: LANCAM Initialization Code
10
Rev. 0.8 Draft
MUSIC [ MUSIC SEMICONDUCTORS ]
