MU9C8328A Ethernet Interface
SWITCHING CHARACTERISTICS
No
1
Symbol Parameter (all times in nanoseconds)
Max
50
Min
Typ
Notes
tKHKH
tKHKL
tKLKH
tKHCH
tCHKH
tCHCH
tCHCL
tCLCH
tSLKH
tSHKH
SYSCLK Period
30
2
SYSCLK HIGH Pulse Width
0.6 · tKHKH
0.6 · tKHKH
0.4 · tKHKH
3
SYSCLK LOW Pulse Width
0.4 · tKHKH
4
SYSCLK HIGH to SERCLK HIGH Set-up Time
SERCLK HIGH to SYSCLK HIGH Set-up Time
SERCLK Period
0
0
5
6
100
7
SERCLK HIGH Pulse Width
0.6 · tCHCH
0.6 · tCHCH
0.4 · tCHCH
8
SERCLK LOW Pulse Width
0.4 · tCHCH
9
Chip or Address Select LOW to SYSCLK HIGH Set-up
Chip or Address Select HIGH to SYSCLK HIGH Set-up
10
10
2
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
tSLSH1 Chip or Address Select LOW Pulse Width - Write Cycle
2 · tKHKH
5
tAVSL
tSLAX
tWVKH
Address Bus VALID to Address Select LOW Set-up
Address Select LOW to Address Bus INVALID Hold
Write Enable LOW to SYSCLK HIGH Set-up Time
10
10
tWVWX Write Enable LOW Pulse Width
tKHKH
10
tKHWH SYSCLK HIGH to Write Enable HIGH Hold Time
tDVKH
tKHDX
tKHRL
tKHRH
Data VALID to SYSCLK HIGH Set-up Time
SYSCLK HIGH to Data INVALID Hold Time
SYSCLK HIGH to Ready LOW Delay Time
SYSCLK HIGH to Ready HIGH Delay Time
10
10
30
30
tRLRH1 Ready LOW Pulse Width-Write Cycle
tKHKH
tTHCH
tCHTL
tYLTV
SERDAT HIGH to SERCLK HIGH Set-up Time
SERCLK HIGH to SERDAT LOW Hold Time
NetReady LOW to SERDAT HIGH Set-up Time
SYSCLK HIGH to REJECT LOW Delay Time
10
10
10
3
4
tKHJL
11 · tKHKH
tKHDZ1 Chip or Address Select LOW Pulse Width-Read Cycle
2 · tKHKH
3 · tKHKH
tKHDV
tKHDZ
SYSCLK HIGH to Data VALID Delay Time
SYSCLK HIGH to Data HIGH-Z Delay Time
30
30
7
8
tRLRH2 Ready LOW Pulse Width-CAM Write Cycle
tKHEL
tKHEH
tKHGV
tKHGX
tEHML
tRHSH
tSHDZ
tKHDX
tKHDV
tELQV
tEHQZ
SYSCLK HIGH to CAM Enable LOW Delay Time
SYSCLK HIGH to CAM Enable HIGH Delay Time
SYSCLK HIGH to CAM Controls VALID Delay Time
SYSCLK HIGH to CAM Controls INVALID Delay Time
CAM Enable HIGH to Match Flag LOW Delay Time
Ready HIGH to Chip or Address Select HIGH Set-up
Chip or Address Select HIGH to Data HIGH-Z Delay
SYSCLK HIGH to Data Bus Active-Read
30
30
30
30
30
5
5
6
5
5
30
SYSCLK HIGH to Data Bus VALID Delay Time
CAM Enable LOW to DQ Bus VALID-Read
50
85
20
6
6
CAM Enable HIGH to DQ Bus HIGH-Z
Rev. 0.8 Draft
12
MUSIC [ MUSIC SEMICONDUCTORS ]
