MU9C8328A Ethernet Interface
NOTES
1.
2.
3.
4.
5.
6.
7.
8.
9.
-1.0 Volts for a duration of 10 ns measured at the 50% amplitude points for input-only lines (Figure 7).
If this timing parameter is violated, the read or write cycle will start one SYSCLK later (assuming /AS or /CS is held).
Before first network data pulse.
From the SYSCLK that strobed the last DA or SA segment into the LANCAM.
LANCAM Controls include /W, /CM, and /EC.
See the LANCAM Handbook for additional information on LANCAM Timing Specs.
With load specified in Figure 5.
With load specified in Figure 6.
Pin A(3)
Clock Timing
1
2
3
SYSCLK
4
5
SERCLK
8
7
6
Processor Interface Write Cycle
SYSCLK
/CS
10
10
9
11
9
11
/AS
12
13
A(2-0)
14
16
15
/WE
17
18
D(15-0)
READY
19
20
21
13
Rev. 0.8 Draft
MUSIC [ MUSIC SEMICONDUCTORS ]
