MU9C2480A/L
FUNCTIONAL DESCRIPTION Continued
in the vertically cascaded chain to supply its own address
in the event of a match, eliminating the need for an external
priority encoder to calculate the complete Match address
at the expense of the ripple-through time to resolve the
Highest-Priority match. The Full flag daisy-chaining allows
Associative writes using a Move to Next Free Address
instruction which does not need a supplied address.
A Page Address register in each device simplifies vertical
expansion in systems using more than one LANCAM. This
register is loaded with a specific device address during
system initialization, which then serves as the higher-order
address bits. A Device Select register allows the user to
target a specific device within a vertically cascaded system
by setting it equal to the Page Address Register value, or
to address all the devices in a string at the same time by
setting the Device Select value to FFFFH.
Figure 1b on page 7 shows an external PLD implementation
of a simple priority encoder that eliminates the daisy chain
ripple-through delays for systems requiring maximum
performance from many CAMs.
Figure 1a on page 7 shows expansion using a daisy chain.
Note that system flags are generated without the need for
external logic. The Page Address register allows each device
OPERATIONAL CHARACTERISTICS
Comparand register, Mask Register 1, Mask Register 2, and
the Memory array.
Throughout the following, “aaaH” represents a three-digit
hexadecimal number “aaa,” while “bbB” represents a two-
digit binary number “bb.” All memory locations are written
to or read from in 16-bit segments. Segment 0 corresponds to
the lowest order bits (bits 15–0) and Segment 3 corresponds
to the highest order bits (bits 63–48).
The default destination for Command Write cycles is the
Instruction decoder, while the default source for Command
Read cycles is the Status register.
Temporary Command Override (TCO) instructions provide
access to the Control register, the Page Address register,
the Segment Control register, the Address register, the Next
Free Address register, and Device Select register. TCO
instructions are only active for one Command Read or Write
cycle after being loaded into the Instruction decoder.
THE CONTROL BUS
Refer to the Block Diagram on page 1 for the following
discussion. The inputs Chip Enable (/E), Write Enable (/W),
Command Enable (/CM), and Enable Daisy Chain (/EC) are
the primary control mechanism for the LANCAM. The /EC
input of the Control bus enables the /MF Match flag output
when LOW and controls the daisy chain operation.
Instructions are the secondary control mechanism. Logical
combinations of the Control Bus inputs, coupled with the
execution of Select Persistent Source (SPS), Select Persistent
Destination (SPD), and Temporary Command Override
(TCO) instructions allow the I/O operations to and from
the DQ15–0 lines to the internal resources, as shown in
Table 3 on page 9.
The data and control interfaces to the LANCAM are
synchronous. During a Write cycle, the Control and Data
inputs are registered by the falling edge of /E. When writing
to the persistently selected data destination, the Destination
Segment counter is clocked by the rising edge of /E. During
a Read cycle, the Control inputs are registered by the falling
edge of /E, and the Data outputs are enabled while /E is
LOW. When reading from the persistently selected data
source, the Source Segment counter is clocked by the rising
edge of /E.
The Comparand register is the default source and
destination for Data Read and Write cycles. This default
state can be overridden independently by executing a Select
Persistent Source or Select Persistent Destination
instruction, selecting a different source or destination for
data. Subsequent Data Read or Data Write cycles will
access that source or destination until another SPS or SPD
instruction is executed. The currently selected persistent
source or destination can be read back through a TCO PS
or PD instruction. The sources and destinations available
for persistent access are those resources on the 64-bit bus:
THE REGISTER SET
The Control, Segment Control, Address, Mask Register 1,
and the Persistent Source and Destination registers are
duplicated, with one set termed the Foreground set, and
the other the Background set. The active set is chosen by
issuing Select Foreground Registers or Select Background
Registers instructions. By default, the Foreground set is
Rev. 1a
6
MUSIC [ MUSIC SEMICONDUCTORS ]
