MU9C2480A/L
FUNCTIONAL DESCRIPTION Continued
Data can be moved from one of the data registers (CR, MR1, or
MR2) to a memory location that is based on the results of the
last comparison (Highest-Priority Match or Next Free), or to
an absolute address, or to the location pointed to by the active
Address register. Data can also be written directly to the
memory from the DQ bus using any of the above addressing
modes. The Address register may be directly loaded and may
be set to increment or decrement, allowing DMA-type reading
or writing from memory.
which bits in the destination will be updated. If a bit is
HIGH in the mask register, the corresponding bit of the
destination is unchanged.
The match line associated with each memory address is fed
into a priority encoder where multiple responses are
resolved, and the address of the highest-priority responder
(the lowest numerical match address) is generated. In LAN
applications, a multiple response might indicate an error. In
other applications the existence of multiple responders may
be valid.
Two sets of configuration registers (Control, Segment
Control, Address, Mask Register 1, and Persistent Source
and Destination) are provided to permit rapid context
switching between foreground and background activities.
The currently active set of configuration registers controls
writes, reads, moves, and compares. The foreground set
would typically be pre-loaded with values useful for
comparing input data, often called filtering, while the
background set would be pre-loaded with values useful for
housekeeping activities such as purging old entries.
Moving from the foreground task of filtering to the
background task of purging can be done by issuing a single
instruction to change the current set of configuration
registers. The match condition of the device is reset
whenever the active register set is changed.
Four input control signals and commands loaded into an
instruction decoder control the LANCAM. Two of the four
input control signals determine the cycle type. The control
signals tell the device whether the data on the I/O bus
represents data or a command, and is input or output.
Commands are decoded by instruction logic and control
moves, forced compares, validity bit manipulations, and
the data path within the device. Registers (Control, Segment
Control, Address, Next Free Address, etc.) are accessed
using Temporary Command Override instructions. The data
path from the DQ bus to/from data resources (comparand,
masks, and memory) within the device are set until changed
by Select Persistent Source and Destination instructions.
The active Control register determines the operating
conditions within the device. Conditions set by this
register’s contents are reset, enable or disable Match flag,
enable or disable Full flag, CAM/RAM partitioning, disable
or select masking conditions, disable or select auto-
incrementing or -decrementing the Address register, and
select Standard or Enhanced modes. The active Segment
Control register contains separate counters to control the
writing of 16-bit data segments to the selected persistent
destination, and to control the reading of 16-bit data
segments from the selected persistent source.
After a Compare cycle (caused by either a data write to the
Comparand or mask registers, a write to the Control register,
or a forced compare), the Status register contains the
address of the Highest-Priority Matching location in that
device, concatenated with its page address, along with
flags indicating internal match, multiple match, and full.
When the Status register is read with a Command Read
cycle, the device with the Highest-Priority match will
respond, outputting the System Match address to the DQ
bus. The internal Match (/MA) and Multiple Match (/MM)
flags are also output on pins. Another set of flags (/MF
and /FF) that are qualified by the match and full flags of
previous devices in the system are also available directly
on output pins, and are independently daisy-chained to
provide System Match and Full flags in vertically cascaded
LANCAM arrays. In such arrays, if no match occurs during
a comparison, read access to the memory and all the
registers except the Next Free register is denied to prevent
device contention. In a daisy chain, all devices will respond
to Command and Data Write cycles, depending on the
conditions shown in Tables 5a and 5b on page 12, unless
the operation involves the Highest-Priority Match address
or the Next Free address; in which case, only the specific
device having the Highest-Priority match or the Next Free
address will respond.
There are two active mask registers at any one time, which
can be selected to mask comparisons or data writes. Mask
Register 1 has both a foreground and background mode to
support rapid context switching. Mask Register 2 does not
have this mode, but can be shifted left or right one bit at a
time. For masking comparisons, data stored in the active
selected mask register determines which bits of the
comparand are compared against the valid contents of the
memory. If a bit is set HIGH in the mask register, the same
bit position in the Comparand register becomes a “don’t
care” for the purpose of the comparison with all the memory
locations. During a Data Write cycle or a MOV instruction,
data in the specified active mask register can also determine
5
Rev. 1a
MUSIC [ MUSIC SEMICONDUCTORS ]
