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MU9C2480L-12DC 参数 Datasheet PDF下载

MU9C2480L-12DC图片预览
型号: MU9C2480L-12DC
PDF下载: 下载PDF文件 查看货源
内容描述: [Content Addressable SRAM, 2KX64, 85ns, CMOS, PQCC44]
分类和应用: 局域网双倍数据速率静态存储器内存集成电路
文件页数/大小: 28 页 / 144 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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MU9C2480A/L  
GENERAL DESCRIPTION  
The MU9C2480A and MU9C2480L LANCAMs are 2048 x  
64-bit content-addressable memories (CAMs), with a 16-bit  
wide interface. They are pin compatible with all devices in the  
MUSICLANCAMfamily.  
data in a short, constant time period, no matter how many  
entries are in the database. The ability to search data words  
up to 64 bits wide allows large address spaces to be  
searched rapidly and efficiently. A patented architecture  
links each CAM entry to associated data and makes this  
data available for use after a successful compare operation.  
Content-addressable memories, also known as associative  
memories, operate in the converse way to random access  
memories (RAM). In RAM, the input to the device is an  
address and the output is the data stored at that address.  
In CAM, the input is a data sample and the output is a flag  
to indicate a match and the address of the matching data.  
As a result, CAM searches large databases for matching  
The MUSIC LANCAMs are ideal for address filtering and  
translation applications in LAN switches and routers. The  
LANCAMs are also well suited to encryption, database  
accelerators, and image processing.  
OPERATIONAL OVERVIEW  
To use the LANCAM, the user loads the data into the  
Comparand register, which is automatically compared to all  
valid CAM locations. The device then indicates whether  
or not one or more of the valid CAM locations contains  
data that matches the target data. The status of each CAM  
location is determined by two validity bits at each memory  
location. The two bits are encoded to render four validity  
conditions: Valid, Skip, Empty, and Random Access, shown  
in Table 1. The memory can be partitioned into CAM and  
associated RAM segments on 16-bit boundaries, but by  
using one of the two available mask registers, the CAM/RAM  
partitioning can be set at any arbitrary size between zero  
and 64 bits.  
Comparand, and mask registers automatically triggers a  
compare. Compares may also be initiated by a command  
to the device. Associated RAM data is available  
immediately after a successful compare operation. The  
Status register reports the results of compares including  
all flags and addresses. Two mask registers are available  
and can be used in two different ways: to mask  
comparisons or to mask data writes. The random access  
validity type allows additional masks to be stored in the  
CAM array where they may be retrieved rapidly.  
A simple four-wire control interface and commands  
loaded into the Instruction decoder control the device.  
A powerful instruction set increases the control flexibility  
and minimizes software overhead. Additionally,  
dedicated pins for match and multiple-match flags  
enhance performance when the device is controlled by a  
state machine. These and other features make the  
LANCAM a powerful associative memory that drastically  
reduces search delays.  
The LANCAM’s internal data path is 64 bits wide for rapid  
internal comparison and data movement. Vertical cascading  
of additional LANCAMs in a daisy chain fashion extends  
the CAM memory depth for large databases. Cascading  
requires no external logic. Loading data to the Control,  
/W  
/CM  
LOW  
HIGH  
LOW  
HIGH  
Cycle Type  
Skip Bit  
Empty Bit  
Entry Type  
Valid  
LOW  
LOW  
HIGH  
HIGH  
Command Write Cycle  
Data Write Cycle  
Command Read Cycle  
Data Read Cycle  
0
0
1
1
0
1
0
1
Empty  
Skip  
RAM  
Table 2: I/O Cycles  
Table 1: Entry Types vs. Validity Bits  
Rev. 1a  
2
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