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MU9C2480L-12DC 参数 Datasheet PDF下载

MU9C2480L-12DC图片预览
型号: MU9C2480L-12DC
PDF下载: 下载PDF文件 查看货源
内容描述: [Content Addressable SRAM, 2KX64, 85ns, CMOS, PQCC44]
分类和应用: 局域网双倍数据速率静态存储器内存集成电路
文件页数/大小: 28 页 / 144 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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MU9C2480A/L  
OPERATIONAL CHARACTERISTICS Continued  
simultaneously by setting DS=FFFFH. Since reading is  
prohibited when DS=FFFFH (except for the device with  
a match), for a diagnostic operation you need to select a  
specific device by setting DS=PA for the desired device  
to be able to read from it. Refer to Tables 5a and 5b on  
page 12 for preconditions for reading and writing.  
Vertically Cascaded System Initialization  
Table 6 shows an example of code that initializes a daisy-  
chained string of LANCAM devices. The initialization  
example shows how to set the Page Address registers of  
each of the devices in the chain through the use of the  
Set Full Flag instruction, and how the Control registers  
and Segment counters of all the LANCAM devices are  
set for a typical application. Each Page Address register  
must contain a unique value (not FFFFH) to prevent bus  
contention.  
Initialization for a single LANCAM is similar. The Device  
Select register in this case is usually set to equal the  
Page Address register for normal operations. Also, the  
dedicated /MA flag output can be used instead of /MF,  
allowing /EC to be tied HIGH.  
For typical daisy chain operation, data is loaded into the  
Comparand registers of all the devices in a string  
Notes  
Control bus  
Cycle type  
Op-Code  
Comments  
on DQ Bus  
/E /CM /W /EC  
Command read  
Command write  
Command write  
Commandwrite  
Command write  
Command write  
Command write  
Command write  
Clear power-up anomalies.  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
L
L
L
L
L
L
L
TCO DS  
FFFFH  
TCO CT  
0000H  
TCO PA  
nnnnH  
SFF  
Target Device Select Register to disable local device selction.  
Disable Device Select feature.  
Target Control register for reset.  
Causes Reset.  
1
2
Target Page Address register to set page for cascaded operation.  
Page Address value.  
2
H
H
Set Full flag; allows access to next device (repeat previous  
two cycles plus this one for each device in chain.  
Target Control register for reset of Full flags, but not Page address.  
Causes Reset.  
2,3  
Command write  
Commandwrite  
Command write  
Command write  
Command write  
Command write  
TCO CT  
0000H  
1
1
4
4
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
TCO CT  
8040H  
Target Control register for initial values.  
Control register value.  
TCO SC  
3808H  
Target Segment Count Control register  
H
H
Set both Segment Counters to write to Segment 1, 2 and 3, and  
read from Segment 0.  
4
Set Data Reads from Segment 0 of the Highest-Priority match.  
Command write  
H
SPS M@HM  
L
L
L
Notes:  
1. Toggling the /Reset pin generates the same effect as this reset of the Control register, but good programming  
practice dictates a software reset for initialization to account for all possible prior conditions.  
2. This instruction may be omitted for a single LANCAM application.  
3. The last SFF will cause the /FF pin in the last chip in a daisy chain to go LOW. In a daisy chain, DS needs to be set equal to PA  
to read out a particular chip prior to a match condition.  
4. A typical LANCAM control environment: Enable match flag; Enable full flag; 48 CAM bits, 16 RAM bits; Disable comparison  
masking; and Enable address increment. See Table 8 on page 21 for Control Register bit assignments.  
Table 6: Example Initialization Routine  
Rev. 1a  
16