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MU9C2480L-12DC 参数 Datasheet PDF下载

MU9C2480L-12DC图片预览
型号: MU9C2480L-12DC
PDF下载: 下载PDF文件 查看货源
内容描述: [Content Addressable SRAM, 2KX64, 85ns, CMOS, PQCC44]
分类和应用: 局域网双倍数据速率静态存储器内存集成电路
文件页数/大小: 28 页 / 144 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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MU9C2480A/L  
OPERATIONAL CHARACTERISTICS Continued  
/E  
/W  
/CM  
/EC  
DQ15-0  
DA TA OU T  
Figure 3: Read Cycle  
/E  
/W  
/C M  
/EC  
D Q15–0  
Figure 4: Write Cycle  
ASS OC IAT ED D ATA  
R EA D C YCL E  
STA TU S R EAD  
C YC L E  
COM PAR AN D W RIT E  
C YC L E  
/E  
/CM  
/W  
DQ15–0  
DA TA  
DA TA  
DA TA  
/EC  
/M F  
M AT CH FLA G VA LID  
/M A, /M M  
/M A A ND /M M FL AGS UPD AT ED  
Figure 5: Cycle to Cycle Timing Example  
forced compare against “Empty” locations automatically  
masks all 64 bits of data to find all locations with the validity  
bits set to “Empty,” while the other forced compares are  
only masked as selected in the Control register.  
Automatic compares perform a compare of the contents of the  
Comparand register against Memory locations that are tagged  
as “Valid,” and occur whenever the following happens:  
Ø The Destination Segment counter in the Segment  
Control register reaches its end limit during writes to  
the Comparand or mask registers.  
VERTICAL CASCADING  
Ø After a command write of a TCO CT is executed (except  
for a software reset), so that a compare is executed  
with the new settings of the Control register.  
LANCAMs can be vertically cascaded to increase system  
depth. Through the use of flag daisy-chaining, multiple  
devices will respond as an integrated system. The flag  
daisy chain allows all commands to be issued globally,  
with a response only in the device containing the Highest-  
Forced compares are initiated by CMP instructions  
using one of the four validity conditions: V, R, S, and E. The  
13  
Rev. 1a