欢迎访问ic37.com |
会员登录 免费注册
发布采购

MU9C2480L-12DC 参数 Datasheet PDF下载

MU9C2480L-12DC图片预览
型号: MU9C2480L-12DC
PDF下载: 下载PDF文件 查看货源
内容描述: [Content Addressable SRAM, 2KX64, 85ns, CMOS, PQCC44]
分类和应用: 局域网双倍数据速率静态存储器内存集成电路
文件页数/大小: 28 页 / 144 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
 浏览型号MU9C2480L-12DC的Datasheet PDF文件第8页浏览型号MU9C2480L-12DC的Datasheet PDF文件第9页浏览型号MU9C2480L-12DC的Datasheet PDF文件第10页浏览型号MU9C2480L-12DC的Datasheet PDF文件第11页浏览型号MU9C2480L-12DC的Datasheet PDF文件第13页浏览型号MU9C2480L-12DC的Datasheet PDF文件第14页浏览型号MU9C2480L-12DC的Datasheet PDF文件第15页浏览型号MU9C2480L-12DC的Datasheet PDF文件第16页  
MU9C2480A/L  
OPERATIONAL CHARACTERISTICS Continued  
Case  
Internal  
/EC(int)  
Internal  
/MA (int)  
External  
/MI  
Device select  
reg.  
Command Data write Command Data read  
write1  
read  
1
2
3
1
1
1
X
X
X
X
X
X
DS=FFFFH  
YES3  
YES3  
NO  
YES4  
YES4  
NO  
NO  
YES  
NO  
NO  
YES  
NO  
DS=PA  
DSFFFFH and  
DSPA  
4
5
62  
0
0
0
X
1
0
0
1
1
X
X
X
NO  
NO  
YES3  
NO  
NO  
YES4  
NO5  
NO5  
YES5  
NO  
NO  
YES  
Table 5a: Standard Mode Device Select Response  
Case  
Internal  
/EC(int)  
Internal  
/MA (int)  
External  
/MI  
Device select  
reg.  
Command Data write Command Data read  
write1  
read  
1
2
3
1
1
1
X
X
X
X
X
X
DS = FFFFH  
DS = PA  
YES3  
YES3  
NO  
YES4  
YES4  
NO  
NO  
YES  
NO  
NO  
YES  
NO  
DS FFFFH  
and DS PA  
4
5
62  
0
0
0
0
1
0
0
X
1
X
X
X
YES3,6  
YES3,6  
YES3  
YES4,7  
YES4,7  
YES4  
NO5  
NO5  
YES5  
NO  
NO  
YES  
Table 5b: Enhanced Mode Device Select Response  
NOTES:  
1. Exceptions are:  
A) A write to the Device Select register is always active in all devices.  
B) A write to the Page Address register is active in the device with /FI LOW and /FF HIGH.  
C) The Set Full Flag (SFF) instruction is active in the device with /FI LOW and /FF HIGH.  
2. If /MF is disabled in the Control register, /MA (Internal) is forced HIGH preventing a Case 6 response.  
3. This is NO for a MOV instruction involving Memory at Next Free address if /FI is HIGH or the device is full.  
4. This is NO if the Persistent Destination is Memory at Next Free address and /FI is HIGH or the device is full.  
5. For a Command Read following a TCO NF instruction, this is YES if the device contains the first empty location in a daisy chain  
(i.e., /FI LOW and /FF HIGH) and NO if it does not.  
6. This is NO for a MOV or VBC instruction involving Memory at Highest-Priority match.  
7. This is NO if the Persistent Destination is Memory at Highest-Priority match.  
The minimum timings for the /E control signal are given in  
such as a Status register or associated data read after a  
the Switching Characteristics section on page 25. Note that  
match. If there is no match in Standard mode, the output  
at minimum timings the /E signal is non-symmetrical, and  
buffers stay Hi-Z, and the daisy chain must be unlocked by  
that different cycle types have different timing requirements,  
as given in Table 7 on page 21.  
taking /EC HIGH during a NOP or other non-functioning  
cycle, as indicated in Table 5a. Figure 6 on page 14 shows  
how the internal /EC timing holds the daisy chain locking  
effect over into the next cycle. In the Enhanced mode, this  
COMPARE OPERATIONS  
NOP is not needed before data or command writes following  
a non-matching compare, as indicated by Table 5b. A  
single-chip system does not require daisy-chained match  
flag operation, hence /EC could be tied HIGH and the /MA  
pin or flag in the Status register used instead of /MF,  
allowing access to the device regardless of the match  
condition.  
During a Compare operation, the data in the Comparand  
register is compared to all locations in the Memory array  
simultaneously. Any mask register used during compares  
must be selected beforehand in the Control register. There  
are two ways compares are initiated: Automatic and Forced  
compares.  
Rev. 1a  
12