MU9C2480A/L
INSTRUCTION SET SUMMARY
Instruction: Select Persistent Destination Cont.
Instruction: Data Move Continued
Operation
Mnemonic
Op-Code
Operation
Mnemonic
Op-Code
Mem. at Highest-Prio. Match, Emp. SPDM@HM,E
012DH
Mask Register 1 from:
Comparand Register
No Operation
Masked by MR1
Masked by MR2
SPD M@HM[MR1],E 016DH
SPD M@HM[MR2],E 01ADH
MOV MR1,CR
NOP 0309H
MOV MR1,MR2
MOV MR1,[AR]
MOV MR1,aaaH
0308H
Mask Register 2
Memory at Address Reg.
Memory at Address
030AH
030CH
0B0CH
030DH
Mem. at Highest-Prio. Match, Skip SPD M@HM,S
012EH
Masked by MR1
Masked by MR2
SPD M@HM[MR1],S 016EH
SPD M@HM[MR2],S 01AEH
Mem. at Highest-Prio. Match MOV MR1,HM
Mem. at High.-Prio. Match, Random SPD M@HM,R
012FH
Mask Register 2 from:
Masked by MR1
Masked by MR2
SPD M@HM[MR1],R 016FH
SPD M@HM[MR2],R 01AFH
Comparand Register
Mask Register 1
No Operation
Memory at Address Reg.
Memory at Address
Mem. at Highest-Prio. Match MOV MR2,HM
MOV MR2,CR
MOV MR2,MR1
NOP
MOV MR2,[AR]
MOV MR2,aaaH
0310H
0311H
0312H
0314H
0B14H
0315H
Mem. at Next Free Addr., Valid SPD M@NF,V
0134H
Masked by MR1
Masked by MR2
SPD M@NF[MR1],V 0174H
SPD M@NF[MR2],V 01B4H
Mem. at Next Free Addr., Empty SPD M@NF,E
0135H
0175H
Memory at Address Register, No Change to Validity bits, from:
Masked by MR1
Masked by MR2
SPD M@NF[MR1],E
SPD M@NF[MR2],E 01B5H
Comparand Register
Masked by MR1
Masked byMR2
Mask Register 1
Mask Register 2
MOV [AR],CR
MOV [AR],CR[MR1] 0360H
MOV [AR],CR[MR2] 03A0H
MOV [AR],MR1
MOV [AR],MR2
0320H
Mem. at Next Free Addr., Skip SPD M@NF,S
0136H
0321H
0322H
Masked by MR1
Masked by MR2
SPD M@NF[MR1],S 0176H
SPD M@NF[MR2],S 01B6H
Memory at Address Register, Location set Valid, from:
Mem. at Next Free Addr., Random SPD M@NF,R
0137H
Comparand Register
Masked by MR1
Masked byMR2
Mask Register 1
Mask Register 2
MOV [AR],CR,V
MOV [AR],CR[MR1],V 0364H
MOV [AR],CR[MR2],V 03A4H
MOV [AR],MR1,V
MOV [AR],MR2,V
0324H
Masked by MR1
Masked by MR2
SPD M@NF[MR1],R 0177H
SPD M@NF[MR2],R 01B7H
0325H
0326H
Instruction: Temporary Command Override
Operation
Mnemonic
TCO CT
TCO PA
TCO SC
TCO NF
TCO AR
TCO DS
TCO PS
TCO PD
Op-Code
0200H
0208H
0210H
0218H
0220H
0228H
0230H
0238H
Memory at Address, No Change to Validity bits, from:
Control Register
Comparand Register
Masked byMR1
Masked byMR2
Mask Register 1
Mask Register 2
MOV aaaH,CR
MOV aaaH,CR[MR1] 0B60H
MOV aaaH,CR[MR2] 0BA0H
MOV aaaH,MR1
MOV aaaH,MR2
0B20H
Page Address Register
Segment Control Register
Read Next Free Address
Address Register
Device Select Register
Read Persistent Source
Read Persistent Destination
0B21H
0B22H
Memory at Address, Location set Valid, from:
Comparand Register
Masked byMR1
Masked byMR2
Mask Register 1
Mask Register 2
MOV aaaH,CR,V
MOVaaaH,CR[MR1],V 0B64H
MOVaaaH,CR[MR2],V 0BA4H
MOV aaaH,MR1,V
MOV aaaH,MR2,V
0B24H
Instruction: Data Move
Operation
Comparand Register from:
No Operation
Mask Register 1
Mask Register 2
Memory at Address Reg.
Masked by MR1
0B25H
0B26H
Mnemonic
Op-Code
NOP
0300H
0301H
0302H
0304H
Memory at Highest-Priority Match, No Change to Validity
bits, from:
MOV CR,MR1
MOV CR,MR2
MOV CR,[AR]
MOV CR,[AR][MR1] 0344H
MOV CR,[AR][MR2] 0384H
Comparand Register
Masked byMR1
Masked byMR2
Mask Register 1
Mask Register 2
MOV HM,CR
0328H
0368H
03A8H
0329H
032AH
MOV HM,CR[MR1]
MOV HM,CR[MR2]
MOV HM,MR1
MOV HM,MR2
Masked by MR2
Memory at Address
Masked by MR1
Masked by MR2
MOV CR,aaaH
MOV CR,aaaH[MR1] 0B44H
MOV CR,aaaH[MR2] 0B84H
0B04H
Memory at Highest-Priority Match, Location set Valid, from:
Comparand Register
Masked byMR1
Masked byMR2
Mask Register 1
Mask Register 2
MOV HM,CR,V
MOV HM,CR[MR1],V 036CH
MOV HM,CR[MR2],V 03ACH
MOV HM,MR1,V
MOV HM,MR2,V
032CH
Mem. at Highest-Prio. Match MOV CR,HM
Masked by MR1
Masked by MR2
0305H
0345H
0385H
MOV CR,HM[MR1]
MOV CR,HM[MR2]
032DH
032EH
19
Rev. 1a
MUSIC [ MUSIC SEMICONDUCTORS ]
