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MU9C8K64-90TDI 参数 Datasheet PDF下载

MU9C8K64-90TDI图片预览
型号: MU9C8K64-90TDI
PDF下载: 下载PDF文件 查看货源
内容描述: MU9C RCP家庭 [MU9C RCP Family]
分类和应用: 存储内存集成电路静态存储器双倍数据速率
文件页数/大小: 35 页 / 1040 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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Control State Descriptions  
MU9C RCP Family  
CONTROL STATE DESCRIPTIONS  
Control State:  
Mnemonic:  
Binary Op-Code:  
/W: HIGH /AV: HIGH PA:AA: n/c Scope: S  
Description: Reads the contents of the Configuration  
register to the DQ31-0 bus. DSC must be LOW.  
Read Configuration Register  
RD FR  
XXX XXX 000 110  
REGISTER READ/WRITE  
Control State:  
Mnemonic:  
No Operation  
NOP Binary  
Binary Op-Code:  
XXX XXX 000 011  
/W: LOW /AV: HIGH PA:AA: n/c Scope: n/a  
Description: No operation. The device performs no  
operation during the cycle. No existing states change. DSC  
must be LOW.  
Control State:  
Mnemonic:  
Binary Op-Code:  
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS  
Description: Writes data from the DQ31-0 bus to the  
Device Select register. The write is masked by the contents  
of Mask Register nnn. When nnn=000 no mask is used;  
when masking is selected, only bits in the addressed  
location that correspond to LOW values in the selected  
mask register are updated. DSC must be LOW.  
Write Device Select Register  
WR DS{MRnnn}  
XXX nnn 001 000  
Control State:  
Mnemonic:  
Read Next Free Address  
RD NFA  
Binary Op-Code:  
XXX XXX 000 011  
/W: HIGH /AV: HIGH PA:AA: n/c Scope: NFD  
Description: Reads the value of the Next Free address on  
the DQ11-0/DQ12-0 bus. In a vertically cascaded system  
this will be in the device whose /FI=LOW and /FF=HIGH,  
and at the highest-priority location whose Validity bit is  
set HIGH. This value is the address of the location where a  
subsequent Write at Next Free Address cycle will be  
written. The Page address of the device value is output  
DQ19-16; DQ31-20 are LOW. DSC must be LOW.  
Control State:  
Mnemonic:  
Binary Op-Code:  
/W: HIGH AV: HIGH PA:AA: n/c Scope: S  
Description: Reads the contents of the Device Select  
register to the DQ31-0 bus. DSC must be LOW.  
Read Device Select Register  
RD DS  
XXX XXX 001 000  
Control State:  
Mnemonic:  
Write Address Register  
WR AR{MRnnn}  
Control State:  
Mnemonic:  
Binary Op-Code:  
/W: HIGH /AV: HIGH PA:AA: n/c Scope: HPD/S  
Description: Reads the contents of the Status register to  
the DQ31-0 bus. After a Comparison or Read/Write at  
Highest-Priority Matching Address cycle only the  
highest-priority device with a match responds to this  
Read Status Register  
RD SR  
XXX XXX 000 111  
Binary Op-Code:  
XXX nnn 000 100  
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS  
Description: Writes data from the DQ31-0 bus to the  
Address register. The write is masked by the contents of  
Mask Register nnn. When nnn=000 no mask is used; when  
masking is selected, only bits in the addressed location  
that correspond to LOW values in the selected mask  
register are updated. DSC must be LOW.  
control state; in the event of  
a mismatch, the  
Control State:  
Mnemonic:  
Binary Op-Code:  
/W: HIGH /AV: HIGH PA:AA: n/c Scope: S  
Description: Reads the contents of the Address register to  
the DQ31-0 bus. DSC must be LOW.  
Read Address Register  
RD AR  
XXX XXX 000 100  
lowest-priority device responds. After a random access  
Read or Write cycle into the Memory array, RD SR will  
take place in any selected device. DSC must be LOW.  
Control State:  
Mnemonic:  
Write Comparand Register  
WRs CR{MRnnn}  
Binary Op-Code:  
XXX nnn 000 101  
Control State:  
Mnemonic:  
Binary Op-Code:  
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS  
Description: Writes data from the DQ31-0 bus to the  
Configuration register. The write is masked by the  
contents of Mask Register nnn. When nnn=000 no mask is  
used; when masking is selected, only bits in the addressed  
location that correspond to LOW values in the selected  
mask register are updated. DSC must be LOW.  
Write Configuration Register  
WR FR{MRnnn}  
XXX nnn 000 110  
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS  
Description: Writes data from the DQ31-0 bus to bits  
31-0 (DSC LOW) or 63-32 (DSC HIGH) of the  
Comparand register. The write is masked by bits 31-0  
(DSC LOW) or 63-32 (DSC HIGH) of Mask Register nnn.  
When nnn=000 no mask is used; when masking is  
selected, only bits in the addressed location that  
correspond to LOW values in the selected mask register  
are updated.  
Rev. 8.04  
19  
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