Register Descriptions
MU9C RCP Family
Status Register
Each 64-bit location in the Address Database array has one
extra bit, the Validity bit, which is used to indicate whether
the location is empty or has valid contents. When the
Validity bit is HIGH, the location is empty and is not
compared during Comparison cycles; when it is LOW the
contents are valid and will be compared during a
Comparison cycle. The Validity bits are set or reset during
Write cycles through the /VB line. The Validity bit of a
location is accessed on the /VB line during a Read cycle.
The Validity bits can be set and reset through control
states. The Validity bits also are used in the generation of
the next free address value.
The 32-bit Status register holds the results of the most
recent control state that caused the PA:AA lines to change.
It is intended for use in Software Control mode where
results of an operation are read from the MU9C RCP
through the DQ31-0 lines. Bit SR30 holds the Match flag,
/MF, which goes LOW when there is a match in the
Address Database. Bit SR29 holds an internal version of
the Multiple Match flag, /MM, which is LOW if there is a
multiple match in the particular device; note that this is not
a system-level multiple match indication. Bit SR28 holds
the Full flag, /FF, which goes LOW when all the Address
Database locations are set valid, and the /FI line is LOW.
Bits SR25-24 indicate the type of result held in the Active
Address field: Match address, Memory Access address, or
Reset state. Bits SR19-16 hold the Page address, PA3-0,
for the device. Bits SR12-0 hold the Active address,
identical to that on the AA bus. All other bits are reserved
and are set LOW. See Table 5 on page 26.
Address Database Access
Data is written to or read from the Address Database array
either randomly by address, or associatively by
comparison and next free address. Random addressing can
be either direct with the address on the DSC and AC12-0
lines (/AV=LOW) or indirect with the address held in the
Address register. Address Database access is controlled
through the control states on the DSC and AC12-0 lines
(/AV=HIGH) in Hardware Control mode, or through the
Instruction register in Software Control mode.
Next Free Address Register
The 32-bit Next Free Address register holds the
highest-priority address that has its Validity bit set empty
(HIGH). System-level prioritization ensures that only the
device with the highest-priority empty address in a
vertically cascaded system will respond to a Read Next
Free Address Register Control state. Bits NF19-16 hold
the device Page address, PA3-0. Bits NF12-0 hold the next
free address value. All other bits are reserved, and are set
LOW. See Table 6 on page 26.
Chip Select
There are two methods of selecting the MU9C RCP:
through Hardware control inputs /CS1 and /CS2, and
through software control through the Data Select register.
Chip Select Inputs
The Chip Select lines /CS1 and /CS2 enable the MU9C
RCP to participate in a control cycle. If either /CS1 or
/CS2 are LOW the device is selected. By connecting all
the /CS1 lines together in a multi-device system, and
decoding the lines to each individual device's /CS2 line,
control states can operate locally within a single device or
globally in all devices. Control states can be broadcast to
all devices within the system by pulling the /CS1 lines
LOW, for operations such as Write Comparand register;
individual devices can be selected to respond to a control
state such as Write at Address by pulling a single decoded
/CS2 line LOW.
Device Select Register
The 32-bit Device Select register is used for software
selection of the MU9C RCP. A particular device is selected
when the value in bits DS3-0 are the same as the Page
Address value PA3-0 and the Device Select Enable bit,
DS8, is set LOW. Setting DS8 HIGH prevents the Device
Select register from enabling the MU9C RCP. All other bits
are reserved and should be set LOW. See Table 7.
Instruction Register
In Software Control mode, control states are written to the
32-bit Instruction register instead of being fed to the
MU9C RCP through the DSC and AC11-0 lines. Bits
IR12-0 are equivalent to the DSC and AC11-0 lines and
the control states they invoke are identical to those of the
Hardware Control mode. The remaining bits are reserved
and should be set LOW.
Device Select Register
One dedicated line is needed per device to do local
selection of one device within a multi-device system. In
cases where control lines are at a premium, the Device
Select register can be used as the method of selection. If
Device Select Register bit DS8 is LOW, only the device or
devices whose Page Address value, held in Configuration
Register bits FR3:0, match with the Device Select Register
bits DS3-0 will be selected. Note that the match condition
of the Device Select register is ORed with the state of the
/CS1 and /CS2 lines. If DS8 is HIGH, the device remains
unselected through the Device Select register.
The Address Database
The Address Database is organized as 4096 or 8192 64-bit
locations: location 0000H as the highest-priority location,
and location 0FFFH as the lowest-priority location. Write
cycles to the next free address start at location 0000H
when the MU9C RCP is empty, and continue down to
0FFFH or 1FFFH when it becomes full.
Rev. 8.04
13
MUSIC [ MUSIC SEMICONDUCTORS ]
