MU9C RCP Family
Operational Characteristics
The instruction is persistent, so that all subsequent data
transactions will be executed according to the control state
held in the Instruction register. The results of a
Comparison cycle can be read back from the Status
register, and include PA:AA bus, /MF, /MM, and /FF. The
following sequence of events provides the fastest
operation of the MU9C RCP in Software Control mode:
Software Control
For optimum performance, the AC bus and DSC line
control the MU9C RCP, allowing data transactions
through the DQ31-0 lines during a control cycle. In cases
where the overhead of a separate data load cycle can be
accommodated, the MU9C RCP can be operated through
the Instruction register. The AC bus and DSC line are not
used.
/AV
1
0
Operation
Load ’Compare DQ with CAM’ instruction
Comparand on DQ31-0
Read Status Register
Control through the Instruction register is selected by the
FR27-26 bits of the Configuration register being set
HIGH. The instruction is loaded from the DQ11-0 lines
(with DSC on DQ12) into the Instruction register during a
Write cycle with the /AV line HIGH. The instructions are
directly analogous to the control states for any operation
that does not involve data transfer on the DQ31-0 lines, in
which case the instruction is executed during the same
cycle as the instruction is loaded. To distinguish between
Read and Write control states, DQ13 is used to indicate
which type of instruction should be executed. When DQ13
is LOW at the beginning of the cycle, the instruction
executed is the Write Cycle instruction (/W = LOW when
control state is conveyed on AC bus and DSC); when
DQ13 is HIGH at the beginning of the cycle, the
instruction executed is the Read Cycle instruction (/W =
HIGH when control state is conveyed on the AC bus).
1
0
1
Next Comparand on DQ31-0
Read Status Register, etc.
Note: It is up to the system designer to ensure that the correct
cycle type follows the loading of an instruction in Software
Control mode. If the instruction expects a Read cycle, and a
Write cycle is executed, or vice versa, the function of the MU9C
RCP is undefined. Such an error may lead to data loss, but will
not damage the device physically.
Hardware Control
Direct hardware control using the AC bus and DSC line
enhances performance of the MU9C RCP. The AC bus
inputs determine which CAM location is accessed, and the
DSC determines whether bits 31-0 (DSC LOW) or bits
63-32 (DSC HIGH) are active. The Hardware Control
mode is selected when Configuration Register bits
FR27-26 are set LOW. The AC bus inputs are qualified by
/W, /AV, and /VB. When /AV is LOW, the AC bus and
DSC line carry the address for a random Read or Write
cycle, depending on the state of /W, and /VB carries the
validity of the location. During a Write cycle, /VB is
written to the Validity bit of the addressed location; during
a Read cycle, the validity of the location is read on the /VB
line. When /VB is LOW, the location contains valid data;
when /VB is HIGH the location is empty.
When the instruction calls for data to be written or read
from the DQ31-0 lines, the instruction is loaded into the
Instruction register during the cycle, and the next Data
Read or Write cycle with /AV LOW executes the
instruction using the DQ31-0 bus for the data transaction.
The instruction is persistent; for example, if no other
instruction is loaded into the Instruction Register,
subsequent data transactions with the /AV line LOW will
be executed according to the instruction currently loaded
in the Instruction register. When there is a data access to a
memory location on DQ31-0 associated with the
instruction, the /VB line carries the validity of that
location.
When /AV is HIGH, the AC bus and DSC line carry
address and control information. The DSC line selects
whether bits 31-0 (DSC LOW) or bits 63-32 (DSC HIGH)
participate in the operation. The AC8-6 lines select the
mask register and the AC5-0 lines provide the Op-Code. If
masking is not used, and all random addressing of the
memory is indirect through the Address register, then only
the DSC and AC5-0 lines are needed for full control of the
device.
Instructions that involve data transactions on DQ31-0, and
are therefore executed on a subsequent Read or Write
cycle with the /AV line LOW, are all Read/Write Memory
and Read/Write Register instructions, Read Validity, Write
PA3-0. All other instructions are executed in a single cycle
with the state of DQ13 being interpreted as the state of the
/W line during the equivalent hardware control state.
In applications where a restricted number of control lines
are available, or where speed is not critical, the MU9C
RCP can be controlled in Software Control mode where
the control states are loaded into the Instruction register
through the DQ31-0 lines. The control states are identical
in both Hardware and Software Control modes, although
DQ12 and DQ13 take on special significance in Software
mode.
For Read Cycles with the /AV line HIGH, there is a
Software Control mode. This mode is selected through the
Configuration bits FR27-26. In Software Control mode
(FR27-26 = 0b11) a Read cycle with /AV HIGH accesses
the Status register.
10
Rev. 8.04
MUSIC [ MUSIC SEMICONDUCTORS ]
