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MU9C8K64-90TDI 参数 Datasheet PDF下载

MU9C8K64-90TDI图片预览
型号: MU9C8K64-90TDI
PDF下载: 下载PDF文件 查看货源
内容描述: MU9C RCP家庭 [MU9C RCP Family]
分类和应用: 存储内存集成电路静态存储器双倍数据速率
文件页数/大小: 35 页 / 1040 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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Operational Characteristics  
MU9C RCP Family  
PA:AA Bus After a Random Access Read or Write to  
the CAM  
Active Address Interface PA:AA Bus  
The Active Address interface PA:AA bus carries the  
currently active address. The address source depends on  
the most recent control state that caused it to change. The  
possible address sources that are output on PA:AA bus are:  
Highest-Priority Match address, Next Free address, Read  
address, and Write address.  
After a random Read or Write cycle to the MU9C RCP, the  
PA:AA bus carries the address that was accessed during  
that cycle. Only the device in which the access occurred  
enables its PA:AA bus. All other devices keep their  
PA:AA bus in high-impedance regardless of the state of  
their /OE inputs. Note that the access to the PA:AA bus  
differs in this respect from the operation of the Status  
register, which is accessible in any selected device under  
this particular circumstance.  
PA:AA Bus After a Comparison Cycle  
After  
a
Comparison cycle, or access to the  
Highest-Priority address, the PA:AA bus carries one of the  
following two possible results:  
In the event that the Write cycle was broadcast to multiple  
devices, all devices that have their /OE lines held LOW  
will enable their PA:AA bus. Under this circumstance, it is  
up to the system designer to ensure that only one /OE line  
is driven LOW to prevent bus contention on the PA:AA  
bus.  
The Match address if the Comparison cycle resulted  
in a match in the MU9C RCP. Only the device  
containing the highest-priority match enables its  
PA:AA bus. All other devices with either no match or  
a lower-priority match, as indicated by the Match Flag  
daisy chain, keep their PA:AA bus in high-impedance  
regardless of the state of their /OE inputs.  
PA:AA Bus Conditions of Operation  
During a control state that does not have any effect on  
the device address, such as a Write Register cycle, the  
PA:AA bus remains unchanged. In other words, the  
state of the PA:AA bus persists until another cycle  
causes it to change.  
All 1s if there was no match in the MU9C RCP. The  
lowest-priority device, as indicated by bit FR25 in the  
Configuration register, enables its PA:AA bus and  
provides the source of all 1s. All other devices will  
keep their PA:AA bus in high-impedance regardless  
of the state of their /OE inputs.  
When enabled by /OE being LOW, the PA:AA bus is  
only free to change while /E is HIGH. When /E goes  
LOW the PA:AA bus is latched.  
PA:AA Bus After a Write at Next Free Address Cycle  
The PA:AA bus is enabled when /OE is LOW  
provided that the previous cycle causes them to be  
active. When /OE is HIGH, the PA:AA bus is in  
high-impedance. Note that /OE is asynchronous with  
respect to /E, and is independent of Chip Select from  
either /CS1, /CS2, or through the Device Select  
register, except in the case of non-broadcast random  
Read and Write cycles to the MU9C RCP.  
After a Write at Next Free Address cycle the PA:AA  
carries the address that was written to during that cycle.  
Only the device in which the write occurred enables its  
PA:AA bus. All other devices keep their PA:AA bus in  
high-impedance regardless of the state of their /OE inputs.  
In the event that the system was full prior to the Write at  
Next Free Address cycle being executed, so that the write  
operation was suppressed, the PA:AA carries all 1s. The  
lowest-priority device, as indicated by bit FR25 in the  
Configuration register, enables its PA:AA bus and  
provides the source of all 1s. All other devices keep their  
PA:AA in high-impedance regardless of the state of their  
/OE inputs.  
Rev. 8.04  
11  
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