MU9C RCP Family
Pin Descriptions
/FF (Full Flag, Output)
/RESET
The /FF output indicates when all the memory locations
have their Validity bits set valid (LOW). When there is at
least one location with its Validity bit set HIGH, the /FF
output will be HIGH; when all locations have their
Validity bits set LOW, and the /FI input is LOW, the /FF
output will be LOW. If the /FI input is HIGH, the /FF
output will be HIGH. The state of the /FF line will not
change until after the rising edge of /E during a Write
cycle.
The /RESET input is used to reset the MU9C RCP to a
known state. When the /RESET line is pulled LOW it
causes the MU9C RCP to enter its reset state. After power
is applied to the MU9C RCP, the /RESET line must be
held LOW for a time equal to or greater than the minimum
RESET pulse width before the device can operate
correctly. This pin is internally pulled up.
TCLK (JTAG Test Clock, Input)
The TCLK input is the Test Clock input. This pin is
internally pulled up.
/FI (Full Input, Input)
The /FI input receives full information from the next
higher-priority MU9C RCP in a vertically cascaded
system to provide system-level full information. When the
/FI input is LOW the /FF output will be HIGH if there is at
least one location whose Validity bit is set invalid; when
all locations have their Validity bits set valid, the /FF
output goes LOW. When the /FI input is HIGH, the /FF
output will remain HIGH. The /FF output from one device
is connected to the /FI input of the next lower-priority
device to give system-full indication. The /FI pin of the
highest-priority device must be tied LOW.
TMS (JTAG Test Mode Select, Input)
The TMS input is the Test Mode Select input. This pin is
internally pulled up.
TDI (JTAG Test Data Input, Input)
The TDI input is the Test Data input. This pin is internally
pulled up.
TDO (JTAG Test Data Output, Output)
The TCLK output is the Test Data Output. This pin is
internally pulled up.
/MM (Multiple Match, Open Drain Output)
/TRST (JTAG Reset, Input)
The /MM line indicates that there is a multiple match
within the system. When the /MI input is HIGH, the /MM
line is pulled LOW if there are at least two matches within
the MU9C RCP as a result of the previous Comparison
cycle; when there are less than two matches, the /MM line
floats HIGH. When the /MI input is LOW, the /MM line is
pulled LOW if there are one or more matches within the
MU9C RCP as a result of the previous Comparison cycle;
when there are no matches, the /MM line floats HIGH.
The /MM lines have open-drain outputs, so all /MM lines
within the system are connected together to give
system-level multiple match indication. The state of the
/MM line will not change until after the rising edge of /E
during a Comparison cycle.
The /TRST input is the Reset input, and serves to reset the
Test Access Port circuitry to its reset condition. This pin is
internally pulled up.
VDD, VDDIO, VSS (Positive Power Supply,
Ground)
These pins are the main power supply connections to the
MU9C RCP. VDD and VDDIO must be held at +3.3 Volts
and ± 0.3 Volts relative to the VSS pin, which is at 0 Volts,
system reference potential, for correct operation of the
device.
Note: The TCLK, TMS, TDI, TDO, and /TRST lines are defined
in the IEEE Standard Test Access Port and Boundary-scan
Architecture IEEE Standard. 1149.1-1990 and IEEE Standard.
1149.1a-1993.
6
Rev. 8.04
MUSIC [ MUSIC SEMICONDUCTORS ]
