IDMA Controller AC Electrical Specifications
Table 11-14. IDMA Controller Timing (continued)
All Frequencies
Num
Characteristic
Unit
Min
Max
43
44
45
46
SDACK negation delay from clock low
SDACK negation delay from TA low
SDACK negation delay from clock high
—
—
—
7
12
20
15
—
ns
ns
ns
ns
TA assertion to falling edge of the clock setup time (applies to
external TA)
CLKO
(Output)
41
40
DREQ
(Input)
Figure 11-43. IDMA External Requests Timing Diagram
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
43
DATA
46
TA
(Input)
SDACK
Figure 11-44. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA
46
MPC860 Family Hardware Specifications
MOTOROLA
MOTOROLA [ MOTOROLA ]
