Serial Interface AC Electrical Specifications
Table 11-17. SI Timing (continued)
All Frequencies
Num
Characteristic
Unit
Min
Max
83
L1RCLK, L1TCLK width low (DSC =1)
P + 10
P + 10
—
—
—
ns
ns
ns
3
83a L1RCLK, L1TCLK width high (DSC = 1)
84
85
L1CLK edge to L1CLKO valid (DSC = 1)
30.00
—
4
L1RQ valid before falling edge of L1TSYNC
1.00
L1TCL
K
2
86
87
88
L1GR setup time
42.00
42.00
—
—
—
ns
ns
ns
L1GR hold time
L1CLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0,
DSC = 0)
0.00
1
2
3
4
The ratio SYNCCLK/L1RCLK must be greater than 2.5/1.
These specs are valid for IDL mode only.
Where P = 1/CLKOUT. Thus, for a 25-MHz CLKO1 rate, P = 40 ns.
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.
L1RCLK
(FE=0, CE=0)
(Input)
71
70
71a
72
L1RCLK
(FE=1, CE=1)
(Input)
RFSD=1
75
74
L1RSYNC
(Input)
73
77
L1RXD
(Input)
BIT0
76
78
79
L1ST(4-1)
(Output)
Figure 11-49. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
50
MPC860 Family Hardware Specifications
MOTOROLA
MOTOROLA [ MOTOROLA ]
