Serial Interface AC Electrical Specifications
CLKO
60
61
63
62
TIN/TGATE
(Input)
61
64
65
TOUT
(Output)
Figure 11-48. CPM General-Purpose Timers Timing Diagram
11.5 Serial Interface AC Electrical Specifications
Table 11-17 provides the serial interface timings as shown in Figure 11-49 through
Figure 11-53.
Table 11-17. SI Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
1, 2
70
71
L1RCLK, L1TCLK frequency (DSC = 0)
L1RCLK, L1TCLK width low (DSC = 0)
—
SYNCCLK/2.5 MHz
2
P + 10
P + 10
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
3
71a L1RCLK, L1TCLK width high (DSC = 0)
72
73
74
75
76
77
78
L1TXD, L1ST(1–4), L1RQ, L1CLKO rise/fall time
L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC setup time)
L1CLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold time)
L1RSYNC, L1TSYNC rise/fall time
15.00
—
20.00
35.00
—
—
15.00
—
L1RXD valid to L1CLK edge (L1RXD setup time)
L1CLK edge to L1RXD invalid (L1RXD hold time)
17.00
13.00
10.00
10.00
10.00
10.00
10.00
0.00
—
4
L1CLK edge to L1ST(1–4) valid
45.00
45.00
45.00
55.00
55.00
42.00
78A L1SYNC valid to L1ST(1–4) valid
79
80
L1CLK edge to L1ST(1–4) invalid
L1CLK edge to L1TXD valid
4
80A L1TSYNC valid to L1TXD valid
81
82
L1CLK edge to L1TXD high impedance
L1RCLK, L1TCLK frequency (DSC =1)
—
16.00 or
SYNCCLK/2
MOTOROLA
MPC860 Family Hardware Specifications
49
MOTOROLA [ MOTOROLA ]
