Bus Signal Timing
AS
B43
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
Figure 9-21. Asynchronous External Master—Control Signals Negation Timing
Table 9-7 provides interrupt timing for the MPC860.
Table 9-7. Interrupt Timing
All Frequencies
1
Num
Characteristic
Unit
Min
Max
I39
I40
I41
I42
I43
IRQx valid to CLKOUT rising edge (setup time)
IRQx hold time after CLKOUT
IRQx pulse width low
6.00
2.00
3.00
3.00
—
—
—
—
—
ns
ns
ns
ns
—
IRQx pulse width high
IRQx edge-to-edge time
4 × T
CLOCKOUT
1
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has
no direct relation with the total system interrupt latency that the MPC860 is able to support.
Figure 9-22 provides the interrupt detection timing for the external level-sensitive lines.
CLKOUT
I39
I40
IRQx
Figure 9-22. Interrupt Detection Timing for External Level Sensitive Lines
Figure 9-23 provides the interrupt detection timing for the external edge-sensitive lines.
MOTOROLA
MPC860 Family Hardware Specifications
33
MOTOROLA [ MOTOROLA ]
