Freescale Semiconductor, Inc.
Appendix: 68HC912D60A EEPROM
EEPROM Control Registers
A steady internal self-time clock is required to provide accurate counts
to meet EEPROM program/erase requirements. This clock is generated
via a programmable 10-bit prescaler register. Automatic program/erase
termination is also provided.
In ordinary situations, with crystal operating properly, the steady internal
self-time clock is derived from the input clock source (EXTALi). The
divider value is as in EEDIVH:EEDIVL. In limp-home mode, where the
oscillator clock has malfunctioned or is unavailable, the self-time clock is
derived from the PLL with approximately 1 MHz frequency, with a
predefined divider value of $0023. Program/erase operation is not
guaranteed in limp-home mode. The clock switching function is only
applicable for permanent loss of crystal condition, so the program/erase
will also not be guaranteed when the loss of crystal condition is
intermittent.
It is strongly recommended that the clock monitor is enabled to ensure
that the program/erase operation will be shutdown in the event of loss of
crystal with a clock monitor reset, or switch to a limp-home mode clock.
This will prevent unnecessary stress on the emulated EEPROM during
oscillator failure.
23.4 EEPROM Control Registers
EEDIVH — EEPROM Modulus Divider
$00EE
Bit 7
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
Bit 0
0
0
EEDIV9
EEDIV8
(1)
(1)
RESET:
—
—
1. Loaded from SHADOW word.
EEDIVL — EEPROM Modulus Divider
$00EF
Bit 7
6
5
4
3
2
1
Bit 0
EEDIV7
EEDIV6
EEDIV5
EEDIV4
EEDIV3
EEDIV2
EEDIV1
EEDIV0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
RESET:
—
—
—
—
—
—
—
—
1. Loaded from SHADOW word.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
409
Appendix: 68HC912D60A EEPROM
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