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Background Debug Mode
location at address $0FC0 (write $7F into address $0FC0). Do not
program other bits of the SHADOW byte (location $0FC0);
otherwise some regular EEPROM array locations will not be
visible. At the next reset, the SHADOW byte is loaded into the
EEMCR register. NOBDML bit in EEMCR will be cleared and BDM
will not be operational.
4. Protect the SHADOW byte by setting SHPROT bit in EEPROT
register.
19.4.6 Disabling BDM lockout
Disabling the BDM lockout is only possible in special modes
(SMODN=0) except in special single chip mode. Follow the same steps
as for enabling the BDM lockout, but erase the SHADOW byte.
At the next reset, the SHADOW byte is loaded into the EEMCR register.
NOBDML bit in EEMCR will be set and BDM becomes operational.
NOTE: When the BDM lockout is enabled it is not possible to run code from the
reset vector in special single chip mode.
19.4.7 BDM Registers
Seven BDM registers are mapped into the standard 64-Kbyte address
space when BDM is active. Mapping is shown in Table 19-4.
Table 19-4. BDM registers
Address
$FF00
Register
BDM Instruction Register
BDM Status Register
BDM Shift Register
$FF01
$FF02 - $FF03
$FF04 - $FF05
$FF06
BDM Address Register
BDM CCR Holding Register
• The INSTRUCTION register content is determined by the type of
background command being executed.
• The STATUS register indicates BDM operating conditions.
68HC(9)12D60 — Rev 4.0
MOTOROLA
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