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XC68HC912D60FU8 参数 Datasheet PDF下载

XC68HC912D60FU8图片预览
型号: XC68HC912D60FU8
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 - 冯4.0 [Advance Information - Rev 4.0]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 432 页 / 2948 K
品牌: MOTOROLA [ MOTOROLA ]
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Freescale Semiconductor, Inc.  
Development Support  
SDV — Shifter Data Valid  
Shows that valid data is in the serial interface shift register. Used by  
the BDM firmware.  
0 = No valid data. Shift operation is not complete.  
1 = Valid Data. Shift operation is complete.  
TRACE — Asserted by the TRACE1 command  
CLKSW — Clock Switch  
0 = BDM system operates with BCLK.  
1 = BDM system operates with ECLK.  
The WRITE_BD_BYTE@FF01 command that changes CLKSW  
including 150 cycles after the data portion of the command should be  
timed at the old speed. Beginning with the start of the next BDM  
command, the new clock can be used for timing BDM communications.  
If ECLK rate is slower than BCLK rate, CLKSW is ignored and BDM  
system is forced to operate with ECLK.  
19.4.9 INSTRUCTION - Hardware Instruction Decode  
The INSTRUCTION register is written by the BDM hardware as a result  
of serial data shifted in on the BKGD pin. It is readable and writable in  
Special Peripheral mode on the parallel bus. It is discussed here for two  
conditions: when a hardware command is executed and when a  
firmware command is executed.  
Read and write: all modes  
The hardware clears the INSTRUCTION register if 512 BCLK cycles  
occur between falling edges from the host.  
BIT 7  
H/F  
0
6
DATA  
0
5
R/W  
0
4
BKGND  
0
3
W/B  
0
2
BD/U  
0
1
0
0
BIT 0  
0
0
RESET:  
INSTRUCTION — BDM Instruction Register (hardware command explanation)  
$FF00  
Advance Information  
68HC(9)12D60 — Rev 4.0  
MOTOROLA  
350  
Development Support  
For More Information On This Product,  
Go to: www.freescale.com  
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