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XC68HC912D60FU8 参数 Datasheet PDF下载

XC68HC912D60FU8图片预览
型号: XC68HC912D60FU8
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 - 冯4.0 [Advance Information - Rev 4.0]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 432 页 / 2948 K
品牌: MOTOROLA [ MOTOROLA ]
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Freescale Semiconductor, Inc.  
Multiple Serial Interface  
PF — Parity Error Flag  
Indicates if received data’s parity matches parity bit. This feature is  
active only when parity is enabled. The type of parity tested for is  
determined by the PT (parity type) bit in SCxCR1.  
0 = Parity correct  
1 = Incorrect parity detected  
Bit 7  
6
5
4
3
0
2
0
1
0
Bit 0  
RAF  
SCSWAI  
MDL1(1)  
MDL0(1)  
MIE(1)  
0
RESET:  
0
0
0
0
0
0
0
SC0SR2 — SCI Status Register 2  
1. See Motorola Interconnect Bus for descriptions of these bits.  
$00C5/$00CD  
Read anytime. Write has no meaning or effect.  
SCSWAI — Serial Communications Interface Stop in WAIT Mode  
0 = SCI clock operates normally.  
1 = Halt SCI clock generation when in WAIT mode.  
RAF — Receiver Active Flag  
This bit is controlled by the receiver front end. It is set during the RT1  
time period of the start bit search. It is cleared when an idle state is  
detected or when the receiver circuitry detects a false start bit  
(generally due to noise or baud rate mismatch).  
0 = A character is not being received  
1 = A character is being received  
If enabled with RIE = 1, RAF set generates an interrupt when  
VDDPLL is high.  
Advance Information  
248  
68HC(9)12D60 — Rev 4.0  
Multiple Serial Interface  
MOTOROLA  
For More Information On This Product,  
Go to: www.freescale.com  
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