Freescale Semiconductor, Inc.
EEPROM Memory
8.3 Future EEPROM Support
Design is underway to introduce an improved EEPROM module with
integrated state machine to simplify programming and erase. This will be
introduced on the 68HC912D60A together with 5V programming Flash
EEPROM.
Appendix: 68HC912D60A EEPROM contains detailed information to
assist in software planning for future EEPROM compatibility and
transition to the 68HC912D60A. Read, write and erase algorithms are
fully compatible with the present EEPROM design. The key change
comes in the form of a self timed state machine for erasing & writing
data. This is implemented using a pre-scaler loaded from a new word
register EEDIV ($00EE) - located in a presently unused location this
register can be written without effect, reading the location will return
unpredictable data.
Adding 5 bytes of initialisation code to current software to load EEDIV
(with value appropriate for the application’s crystal frequency, EXTALi)
will help ensure compatibility.
Other new features for performance improvement are disabled at reset
providing a compatible algorithm for modifying the EEPROM.
CAUTION: Other areas for consideration include:
Program/Erase is not guaranteed in Limp home mode. Clock monitor
CME bit must be enabled during program/erase.
Program/erase should not be performed with input clock frequency <250
KHz.
Resonator/crystal frequency tolerance should be better than 2% total for
< 2MHz, 3% total for >= 2MHz.
Successive writes to an EEPROM location must be preceded by an
erase cycle.
To ensure full compatibility it is recommended that all of Appendix:
68HC912D60A EEPROM be reviewed.
Advance Information
116
68HC(9)12D60 — Rev 4.0
EEPROM Memory
MOTOROLA
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