Freescale Semiconductor, Inc.
Flash Memory
Program/Erase Protection Interlocks
7.10 Program/Erase Protection Interlocks
The Flash EEPROM program and erase mechanisms provide maximum
protection from accidental programming or erasure.
The voltage required to program/erase the Flash EEPROM (V ) is
FP
supplied via an external pin. If V is not present, no
FP
programming/erasing will occur. Furthermore, the program/erase
voltage will not be applied to the Flash EEPROM unless turned on by
setting a control bit (ENPE). The ENPE bit may not be set unless the
programming address and data latches have been written previously
with a valid address. The latches may not be written unless enabled by
setting a control bit (LAT). The LAT and ENPE control bits must be
written on separate writes to the control register (FEExxCTL) and must
be separated by a write to the programming latches. The ERAS and LAT
bits are also protected when ENPE is set. This prevents inadvertent
switching between erase/program mode and also prevents the latched
data and address from being changed after a program cycle has been
initiated.
7.11 Stop or Wait Mode
When stop or wait commands are executed, the MCU puts the Flash
EEPROM in stop or wait mode. In these modes the Flash module will
cease erasure or programming immediately. It is advised not to enter
stop or wait modes when programming the Flash array.
CAUTION: The Flash EEPROM module requires a 250nsec delay for wake-up from
STOP mode. If the operating bus frequency is greater than 4MHz, the
Flash cannot be used when recovering from STOP mode when the DLY
bit in the INTCR register is cleared.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
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Flash Memory
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