9 Pulse Accumulator
The MC68HC11A8 has an 8-bit counter that can be configured to operate as a simple event counter or
for gated time accumulation, depending on the PAMOD bit in the PACTL register. The pulse accumu-
lator counter can be read or written at any time.
The port A bit 7 I/O pin can be configured as a clock in event counting mode, or as a gate signal to en-
able a free-running clock (E divided by 64) in gated time accumulation mode.
Table 9 Pulse Accumulator Timing
Common XTAL Frequencies
Selected Crystal
4.0 MHz
1.0 MHz
1000 ns
8.0 MHz
2.0 MHz
500 ns
12.0 MHz
3.0 MHz
333 ns
CPU Clock
Cycle Time
(E)
(1/E)
Pulse Accumulator (in Gated Mode)
6
1 count —
overflow —
64.0 µs
16.384 ms
32.0 µs
8.192 ms
21.33 µs
5.461 ms
(E/2 )
14
(E/2
)
PAOVI
PAOVF
1
INTERRUPT
REQUESTS
PAII
PAIF
2
E ÷ 64 CLOCK
(FROM MAIN TIMER)
TMSK2 INT ENABLES
TFLG2 INTERRUPT STATUS
PAI EDGE
DISABLE
FLAG SETTING
PAEN
OVERFLOW
PACNT 8-BIT COUNTER
MCU PIN
CLOCK
2 1
MUX
:
PA7/
PAI/
OC1
INPUT BUFFER
AND
EDGE DETECTOR
ENABLE
DATA
BUS
OUTPUT
BUFFER
PAEN
FROM
MAIN TIMER
OC1
FROM
DDRA7
PACTL CONTROL
INTERNAL
DATA BUS
PULSE ACC BLOCK
Figure 12 Pulse Accumulator System Block Diagram
MOTOROLA
38
MC68HC11A8
MC68HC11A8TS/D
MOTOROLA [ MOTOROLA ]
