SPR1 and SPR0 — SPI Clock Rate Selects
E-Clock
Divide By
Frequency at
E = 2 MHz (Baud)
SPR [1:0]
00
01
10
11
2
4
1.0 MHz
500 kHz
125 kHz
62.5 kHz
16
32
SPSR — Serial Peripheral Status Register
$1029
Bit 7
SPIF
0
6
WCOL
0
5
0
0
4
3
0
0
2
0
0
1
0
0
Bit 0
MODF
0
0
RESET:
0
SPIF — SPI Transfer Complete Flag
Set when an SPI transfer is complete. Cleared by reading SPSR with SPIF set followed by SPDR ac-
cess.
WCOL — Write Collision
Set when SPDR is written while transfer is in progress. Cleared by SPSR with WCOL set followed by
SPDR access.
MODF — Mode Fault (A Mode Fault Terminates SPI Operation)
Set when SS is pulled low while MSTR = 1. Cleared by SPSR read with MODF set followed by SPCR
write.
SPDR — SPI Data Register
$102A
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
NOTE
SPI is double buffered in, single buffered out.
MC68HC11A8
MC68HC11A8TS/D
MOTOROLA
31
MOTOROLA [ MOTOROLA ]
