cy. When an external system clock signal is applied and the PLL is disabled, V
DDSYN
should be connected to the V
supply. Refer to the SIM Reference Manual (SIMRM/
DD
AD) for more information regarding system clock power supply conditioning.
A voltage controlled oscillator (VCO) generates the system clock signal. To maintain
a 50% clock duty cycle, VCO frequency is either two or four times system clock fre-
quency, depending on the state of the X bit in SYNCR. A portion of the clock signal is
fed back to a divider/counter. The divider controls the frequency of one input to a
phase comparator. The other phase comparator input is a reference signal, either from
the crystal oscillator or from an external source. The comparator generates a control
signal proportional to the difference in phase between the two inputs. The signal is low-
pass filtered and used to correct VCO output frequency.
Filter geometry can vary, depending upon the external environment and required clock
stability. Figure 4-6 shows two recommended filters. XFC pin leakage must be as
specified in APPENDIX A ELECTRICAL CHARACTERISTICS to maintain optimum
stability and PLL performance.
An external filter network connected to the XFC pin is not required when an external
system clock signal is applied and the PLL is disabled. The XFC pin must be left float-
ing in this case.
4
C3
0.1µF
C1
0.1µF
C3
0.1µF
C1
0.1µF
R1
18kΩ
1
XFC
1, 2
XFC
V
DDSYN
C2
0.01µF
C4
C4
0.01µF
0.01µF
V
DDSYN
V
SSI
V
SSI
NORMAL OPERATING
ENVIRONMENT
HIGH-STABILITY OPERATING
ENVIRONMENT
1. Maintain low-leakage on the XFC node. See Appendix A electrical characteristics for more information.
2. Recommended loop filter for reduced sensitivity to low-frequency noise.
16/32 XFC CONN
Figure 4-6 System Clock Filter Networks
The synthesizer locks when VCO frequency is equal to EXTAL frequency. Lock time
is affected by the filter time constant and by the amount of difference between the two
comparator inputs. Whenever comparator input changes, the synthesizer must relock.
Lock status is shown by the SLOCK bit in SYNCR. During power-up, the MCU does
not come out of reset state until the synthesizer locks. Crystal type, characteristic fre-
quency, and layout of external oscillator circuitry affect lock time.
When the clock synthesizer is used, control register SYNCR determines operating fre-
quency and various modes of operation. The SYNCR W bit controls a three-bit pres-
caler in the feedback divider. Setting W increases VCO speed by a factor of four. The
MC68331
SYSTEM INTEGRATION MODULE
MOTOROLA
4-11
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
