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MC68331CFC16 参数 Datasheet PDF下载

MC68331CFC16图片预览
型号: MC68331CFC16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
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Use the following expression to calculate timer period.  
(PIT Modulus)(Prescaler Value)(4)  
PIT Period = ----------------------------------------------------------------------------------------------  
EXTAL Frequency  
Interrupt priority and vectoring are determined by the values of the periodic interrupt  
request level (PIRQL) and periodic interrupt vector (PIV) fields in the periodic interrupt  
control register (PICR).  
Content of PIRQL is compared to the CPU32 interrupt priority mask to determine  
whether the interrupt is recognized. Table 4-6 shows priority of PIRQL values. Be-  
cause of SIM hardware prioritization, a PIT interrupt is serviced before an external in-  
terrupt request of the same priority. The periodic timer continues to run when the  
interrupt is disabled.  
Table 4-6 Periodic Interrupt Priority  
PIRQL  
000  
001  
010  
011  
100  
101  
110  
111  
Priority Level  
Periodic Interrupt Disabled  
Interrupt Priority Level 1  
Interrupt Priority Level 2  
Interrupt Priority Level 3  
Interrupt Priority Level 4  
Interrupt Priority Level 5  
Interrupt Priority Level 6  
Interrupt Priority Level 7  
4
The PIV field contains the periodic interrupt vector. The vector is placed on the IMB  
when an interrupt request is made. The vector number used to calculate the address  
of the appropriate exception vector in the exception vector table. Reset value of the  
PIV field is $0F, which corresponds to the uninitialized interrupt exception vector.  
4.2.12 Low-Power STOP Operation  
When the CPU32 executes the LPSTOP instruction, the current interrupt priority mask  
is stored in the clock control logic, internal clocks are disabled according to the state  
of the STSIM bit in the SIMCR, and the MCU enters low-power stop mode. The bus  
monitor, halt monitor, and spurious interrupt monitor are all inactive during low-power  
stop.  
During low-power stop, the clock input to the software watchdog timer is disabled and  
the timer stops. The software watchdog begins to run again on the first rising clock  
edge after low-power stop ends. The watchdog is not reset by low-power stop. A ser-  
vice sequence must be performed to reset the timer.  
The periodic interrupt timer does not respond to the LPSTOP instruction, but continues  
to run during LPSTOP. To stop the periodic interrupt timer, PITR must be loaded with  
a zero value before the LPSTOP instruction is executed. A PIT interrupt, or an external  
interrupt request, can bring the MCU out of the low-power stop condition if it has a  
higher priority than the interrupt mask value stored in the clock control logic when low-  
power stop is initiated. LPSTOP can be terminated by a reset.  
MOTOROLA  
4-8  
SYSTEM INTEGRATION MODULE  
MC68331  
USER’S MANUAL