Table D-18 Register Bit and Field Mnemonics, (Continued)
Mnemonic
STSIM
SUPV
SW
Name
Stop Mode System Integration Clock
Supervisor/Unrestricted
Software Watchdog Reset
Software Watchdog Enable
Software Watchdog Prescale
Software Watchdog Timing
System Reset
Register Location
SYNCR
GPTMCR, QSMCR, SIMCR
RSR
SWE
SWP
SWT[1:0]
SYS
SYPCR
SYPCR
SYPCR
RSR
T[1:0]
TC
Trace Enable
SR
Transmit Complete
SCSR
TCIE
TDRE
TE
Transmit Complete Interrupt Enable
Transmit Data Register Empty
Transmitter Enable
SCCR1
SCSR
SCCR1
SCCR1
TFLG2
TIE
Transmit Interrupt Enable
Timer Overflow Flag
TOF
TOI
Timer Overflow Interrupt Enable
Transmit Data RAM
TMSK2
QSPI RAM
RSR
TR[0:F]
TST
Test Submodule Reset
Overflow Flag
V
CCR
D
W
Frequency Control (VCO)
Wakeup by Address Mark
Wired-OR Mode for QSPI Pins
Wired-OR Mode for SCI Pins
Wrap Enable
SYNCR
SCCR1
SPCR0
SCCR1
SPCR2
SPCR2
CCR
WAKE
WOMQ
WOMS
WREN
WRTO
X
Wrap To
Extend
X
Frequency Control Bit (Prescale)
Frequency Control (Counter)
Zero Flag
SYNCR
SYNCR
CCR
Y[5:0]
Z
MC68331
USER’S MANUAL
REGISTER SUMMARY
MOTOROLA
D-43
MOTOROLA [ MOTOROLA ]
