Table D-18 Register Bit and Field Mnemonics
Mnemonic
Name
Base Address
Register Location
ADDR[23:11]
AVEC
CSBAR[0:10], CSBARBT
CSOR[0:10], CSORBT
SPCR0
Autovector Enable
BITS
Bits Per Transfer
BITSE
Bits Per Transfer Enable
Block Size
CR[0:F]
BLKSZ
BME
CSBAR[0:10], CSBARBT
SYPCR
Bus Monitor External Enable
Bus Monitor Timing
Upper/Lower Byte Option
Carry Flag
BMT[1:0]
BYTE
SYPCR
CSOR[0:10], CSORBT
CCR
C
CONT
Continue
CR[0:F]
CPHA
Clock Phase
SPCR0
CPOL
Clock Polarity
SPCR0
CPROUT
CPR[2:0]
CPTQP
CSPA0[6:1]
CSPA1[4:0]
CSBOOT
DDE[7:0]
DDF[7:0]
DDRGP[7:0]
DDQS[7:0]
DSACK
DSCK
Capture/Compare Clock Output Enable
Timer Prescaler/PCLK Select Field
Completed Queue Pointer
Chip-Select [6:1]
TMSK2
TMSK2
SPSR
CSPAR0
CSPAR1
CSPAR0
DDRE
Chip-Select [4:0]
D
Boot ROM Chip Select
Port E Data Direction
Port F Data Direction
Port GP Data Direction
Port QS Data Direction
Data Strobe Acknowledge
PCS to SCK Delay
DDRF
DDRGP
DDRQS
CSOR[0:10], CSORBT
CR[0:F]
DSCKL
DT
Delay Before SCK
SPCR1
Delay After Transfer
Length of Delay After Transfer
Input Capture Edge Control
ECLK Divide Rate
CR[0:F]
DTL
SPCR1
EDGE[4:1]
EDIV
TCTL2
SYNCR
ENDQP
EXOFF
EXT
Ending Queue Pointer
External Clock Off
SPCR2
SIMCR
External Reset
RSR
F1A
Force Logic Level One on PWMA
Force Logic Level One on PWMB
Framing Error
PWMC
F1B
PWMC
FE
SCSR
FOC[5:1]
FPWMA
FPWMB
FRZBM
FRZSW
FRZ[1:0]
FRZ[1:0]
HALT
Force Output Compare
Force PWMA Value
Force PWMB Value
Freeze Bus Monitor Enable
Freeze Software Enable
Freeze Response
CFORC
CFORC
CFORC
SIMCR
SIMCR
GPTMCR
QSMCR
SPCR3
Freeze1
Halt
HALTA
HLT
Halt Acknowledge Flag
Halt Monitor Reset
SPSR
RSR
HME
Halt Monitor Enable
HALTA and MODF Interrupt Enable
SYPCR
HMIE
SPCR3
MOTOROLA
D-40
REGISTER SUMMARY
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
