Table D-18 Register Bit and Field Mnemonics, (Continued)
Mnemonic
I4/O5
Name
Register Location
PACNT
Input Capture 4/Output Compare 5
I4/O5F
Input Capture 4/Output Compare 5
Flag
TFLG1
I4/O5I
IARB[3:0]
ICF[3:1]
ICI[3:1]
IDLE
I4/O5 Interrupt Enable
Interrupt Arbitration
TMSK1
GPTMCR, QSMCR, SIMCR
Input Capture Flags
Input Capture Interrupt Enable
Idle-Line Detected
TFLG1
TMSK1
SCSR
ILIE
Idle-Line Interrupt Enable
Interrupt Level for QSPI
Interrupt Level for SCI
Idle-Line Detect Type
Increment Prescaler
Interrupt Vector Number
Interrupt Priority Mask
Interrupt Priority Adjust
Interrupt Priority Level
Interrupt Vector Base Address
Loss of Clock Reset
QSPI Loop Mode
SCCR1
QILR
ILQSPI
ILSCI
QILR
ILT
SCCR1
GPTMCR
QIVR
INCP
INTV[7:0]
IP[2:0]
IPA
SR
ICR
IPL
CSOR[0:10], CSORBT, ICR
ICR
IVBA
D
LOC
RSR
LOOPQ
LOOPS
M
SPCR3
SCCR1
SCCR1
SIMCR
Loop Mode
Mode Select
MM
Module Mapping
MODE
MODF
MSTR
N
Asynchronous/Synchronous Mode
Mode Fault Flag
CSOR[0:10], CSORBT
SPSR
Master/Slave Mode Select
Negative Flag
SPCR0
CCR
NEWQP
NF
New Queue Pointer Value
Noise Error
SPCR2
SCSR
OC1D[5:1]
OC1M[5:1]
OCF[4:1]
OCI[4:1]
OM[5:2]
OL[5:2]
OR
OC1 Data
OC1D
OC1 Mask
OC1M
Output Compare Flags
Output Compare Interrupt Enable
Output Compare Mode Bits
Output Compare Level Bits
Overrun Error
TFLG1
TMSK1
TCTL1
TCTL1
SCSR
PACLK[1:0]
Pulse Accumulator Clock Select
(Gated Mode)
PACNT
PACNT
PAEN
PAIF
Pulse Accumulator Counter
Pulse Accumulator Enable
Pulse Accumulator Flag
PACNT
PACNT
TFLG2
TMSK2
PAII
Pulse Accumulator Input Interrupt
Enable
PAIS
PAI Pin State (Read Only)
Pulse Accumulator Mode
PACNT
PACNT
TFLG2
TMSK2
PAMOD
PAOVF
PAOVI
Pulse Accumulator Overflow Flag
Pulse Accumulator Overflow Interrupt
Enable
PC[6:0]
Port C Data
PORTC
MC68331
USER’S MANUAL
REGISTER SUMMARY
MOTOROLA
D-41
MOTOROLA [ MOTOROLA ]
