Table D-18 Register Bit and Field Mnemonics, (Continued)
Mnemonic
PCLKS
PCS[3:0]
PE
Name
PCLK Pin State (Read Only)
Peripheral Chip Select
Parity Enable
Register Location
PACNT
CR[0:F]
SCCR1
PE[7:0]
PEDGE
PEPA[7:0]
PF
Port E Data
PORTE
Pulse Accumulator Edge Control
Port E Pin Assignment
Parity Error
PACNT
PEPAR
SCSR
PF[7:0]
PFPA[7:0]
PORTGP[7:0]
PIRQL[2:0]
PITM[7:0]
PIV[7:0]
POW
Port F Data
PORTF
Port F Pin Assignment
Port GP Data
PFPAR
PORTGP
PICR
Periodic Interrupt Request Level
Periodic Interrupt Timing Modulus
Periodic Interrupt Vector
Power-Up Reset
PITR
PICR
RSR
PPROUT
PPR[2:0]
PQS[7:0]
PQSPA[6:0]
PT
PWM Clock Output Enable
PWM Prescaler/PCLK Select
Port QS Data
PWMC
PWMC
PORTQS
PQSPAR
SCCR1
Port QS Pin Assignment
Parity Type
D
PTP
Periodic Timer Prescaler Control
Receiver Active
PITR
RAF
SCSR
RDRF
Receive Data Register Full
Receiver Enable
SCSR
RE
SCCR1
RIE
Receiver Interrupt Enable
Receive Data RAM
Reset Enable
SCCR1
RR[0:F]
RSTEN
R/W
QSPI RAM
SYNCR
CSOR[0:10], CSORBT
SCCR1
Read/Write
RWU
Receiver Wakeup
R[8:0]/T[8:0]
S
SCI Receive/Transmit Data
Supervisor/User State
Send Break
SCDR
SR
SBK
SCCR1
SCBR
SCI Baud Rate
SCCR0
SFA
PWMA Slow/Fast Select
PWMB Slow/Fast Select
Show Cycle Enable
LIMP Mode
PWMC
SFB
PWMC
SHEN[1:0]
SLIMP
SLOCK
SLVEN
SPACE
SPBR
SIMCR
SYNCR
SYNCR
SIMCR
Synthesizer Lock
Factory Test Mode Enabled
Address Space Select
Serial Clock Baud Rate
QSPI Enable
CSOR[0:10], CSORBT
SPCR0
SPE
SPCR1
SPIF
QSPI Finished Flag
SPI Finished Interrupt Enable
Stop Mode External Clock
Stop Clocks
SPSR
SPIFIE
STEXT
STOP
SPCR2
SYNCR
GPTMCR
QSMCR
GPTMCR
CSOR[0:10], CSORBT
STOP
Stop Enable
STOPP
STRB
Stop Prescaler
Address Strobe/Data Strobe
MOTOROLA
D-42
REGISTER SUMMARY
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
