D.4.12 SPCR2 — QSPI Control Register 2
$YFFC1C
15
14
13
12
0
11
8
0
7
0
6
0
5
0
4
0
3
0
0
SPIFIE
WREN
WRTO
ENDQP
NEWQP
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt
enable bit. The CPU32 has read/write access to SPCR2, but the QSM has read ac-
cess only. SPCR2 is buffered. New SPCR2 values become effective only after com-
pletion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execution to
restart at the designated location. SPCR2 reads return the value of the register, not
the buffer.
SPIFIE — SPI Finished Interrupt Enable
0 = QSPI interrupts disabled
1 = QSPI interrupts enabled
WREN — Wrap Enable
0 = Wraparound mode disabled
1 = Wraparound mode enabled
D
WRTO — Wrap To
0 = Wrap to pointer address $0
1 = Wrap to address in NEWQP
ENDQP — Ending Queue Pointer
This field contains the last QSPI queue address.
NEWQP — New Queue Pointer Value
This field contains the first QSPI queue address.
D.4.13 SPCR3 — QSPI Control Register 3
SPSR — QSPI Status Register
$YFFC1E
$YFFC1F
15
0
14
0
13
0
12
0
11
0
10
9
8
7
6
5
4
0
3
0
0
LOOPQ
HMIE
HALT
SPIF
MODF
HALTA
CPTQP
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPCR3 contains the loop mode enable bit, halt and mode fault interrupt enables, and
the halt control bit. The CPU has read/write access to SPCR3, but the QSM has read
access only. SPCR3 must be initialized before QSPI operation begins. Writing a new
value to SPCR3 while the QSPI is enabled disrupts operation. SPSR contains infor-
mation concerning the current serial transmission. Only the QSPI can set bits in SPSR.
The CPU reads SPSR to obtain QSPI status information and writes it to clear status
flags.
MOTOROLA
D-34
REGISTER SUMMARY
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
