WOMQ — Wired-OR Mode for QSPI Pins
0 = Outputs have normal MOS drivers.
1 = Pins designated for output by DDRQS have open-drain drivers.
BITS — Bits Per Transfer
The BITS field determines the number of serial data bits transferred.
CPOL — Clock Polarity
0 = The inactive state value of SCK is logic level zero.
1 = The inactive state value of SCK is logic level one.
CPHA — Clock Phase
0 =Data captured on the leading edge of SCK and changed on the following edge
of SCK.
1 =Data is changed on the leading edge of SCK and captured on the following
edge of SCK.
SPBR — Serial Clock Baud Rate
QSPI baud rate is selected by writing a value from 2 to 255 into SPBR. Giving BR a
value of zero or one disables SCK (disable state determined by CPOL).
D
D.4.11 SPCR1 — QSPI Control Register 1
$YFFC1A
15
14
8
7
0
0
SPE
DSCKL
0
DTL
RESET:
0
0
0
0
1
0
0
0
0
0
0
1
0
0
SPCR1 enables the QSPI and specified transfer delays. The CPU32 has read/write
access to SPCR1, but the QSM has read access only to all bits but enable bit SPE.
SPCR1 must be written last during initialization because it contains SPE. Writing a
new value to SPCR1 while the QSPI is enabled disrupts operation.
SPE — QSPI Enable
0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O.
1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI.
DSCKL — Delay before SCK
When the DSCK bit in command RAM is set, this field determines the length of delay
from PCS valid to SCK transition. PCS can be any of the four peripheral chip-select
pins.
DTL — Length of Delay after Transfer
When the DT bit in command RAM is set, this field determines the length of delay after
serial transfer.
MC68331
REGISTER SUMMARY
MOTOROLA
D-33
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
