Table D-16 Effect of DDRQS on QSM Pin Function
QSM Pin
Mode
DDRQS
Bit
Bit
State
Pin Function
MISO
Master
DDQS0
DDQS1
DDQS2
DDQS3
0
1
Serial Data Input to QSPI
Disables Data Input
Slave
Master
Slave
0
Disables Data Output
Serial Data Output from QSPI
Disables Data Output
Serial Data Output from QSPI
Serial Data Input to QSPI
Disables Data Input
1
MOSI
0
1
0
1
1
SCK
Master
Slave
0
Disables Clock Output
Clock Output from QSPI
Clock Input to QSPI
1
0
1
Disables Clock Input
Assertion Causes Mode Fault
Chip-Select Output
PCS0/SS
PCS[3:1]
Master
Slave
0
1
0
QSPI Slave Select Input
Disables Select Input
Disables Chip-Select Output
Chip-Select Output
1
D
Master
Slave
DDQS
[4:6]
0
1
0
Inactive
1
Inactive
2
TXD
Transmit
Receive
DDQS7
None
X
NA
Serial Data Output from SCI
Serial Data Input to SCI
RXD
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes SPI
serial clock SCK.
2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 =1), in which case it
becomes SCI serial output TXD.
DDRQS determines the direction of the TXD pin only when the SCI transmitter is dis-
abled. When the SCI transmitter is enabled, the TXD pin is an output.
D.4.10 SPCR0 — QSPI Control Register 0
$YFFC18
15
MSTR
RESET:
0
14
13
10
9
8
7
0
0
WOMQ
BITS
CPOL CPHA
SP
0
0
0
0
0
0
1
0
0
0
0
1
0
0
SPCR0 contains parameters for configuring the QSPI and enabling various modes of
operation. The CPU has read/write access to SPCR0, but the QSM has read access
only. SPCR0 must be initialized before QSPI operation begins. Writing a new value to
SPCR0 while the QSPI is enabled disrupts operation.
MSTR — Master/Slave Mode Select
0 = QSPI is a slave device.
1 = QSPI is system master.
MOTOROLA
D-32
REGISTER SUMMARY
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
