D.3.25 CSBARBT — Chip Select Base Address Register Boot ROM
$YFFA48
CSBAR[0:10] — Chip Select Base Address Registers $YFFA4C–$YFFA74
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
ADDR
23
ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR
BLKSZ
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
RESET:
0
0
Each chip-select pin has an associated base address register. A base address is the
lowest address in the block of addresses enabled by a chip select. CSBARBT contains
the base address for selection of a bootstrap peripheral memory device. Bit and field
definition for CSBARBT and CSBAR[0:10] are the same, but reset block sizes differ.
ADDR[23:11] — Base Address
This field sets the starting address of a particular address space.
BLKSZ — Block Size
This field determines the size of the block above the base address that is enabled by
the chip select.
D
Table D-11 Block Size Encoding
BLKSZ[2:0]
000
Block Size
2 K
Address Lines Compared
ADDR[23:11]
001
8 K
ADDR[23:13]
010
16 K
ADDR[23:14]
011
64 K
ADDR[23:16]
100
128 K
256 K
512 K
1 M
ADDR[23:17]
101
ADDR[23:18]
110
ADDR[23:19]
111
ADDR[23:20]
D.3.26 CSORBT — Chip Select Option Register Boot ROM
CSOR[0:10] — Chip Select Option Registers
$YFFA4A
$YFFA4E–$YFFA76
15
14
13
12
11
10
9
6
5
4
0
3
1
0
MODE
BYTE
R/W
STRB
DSACK
SPACE
IPL
0
AVEC
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Contain parameters that support bootstrap operations from peripheral memory devic-
es. Bit and field definitions for CSORBT and CSOR[0:10] are the same.
MODE — Asynchronous Bus/Synchronous E-clock Mode
Synchronous mode cannot be used with internally generated autovectors.
0 = Asynchronous mode selected
1 = Synchronous mode selected
BYTE — Upper/Lower Byte Option
The value in this field determines whether a select signal can be asserted.
MC68331
REGISTER SUMMARY
MOTOROLA
D-23
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
