valid, but writes to QSPI RAM or any register are guaranteed valid. STOP is set during
reset. The SCI receiver and transmitter must be disabled before STOP is set. To stop
the QSPI, set the HALT bit in SPCR3, wait until the HALTA flag is set, then set STOP.
FRZ[1:0] — Freeze Control
0 = Ignore the FREEZE signal on the IMB
1 = Halt the QSPI (on a transfer boundary)
FRZ1 determines what action is taken by the QSPI when the FREEZE signal of the
IMB is asserted. FREEZE is asserted whenever the CPU enters background mode.
FRZ0 is reserved for future use.
SUPV — Supervisor/Unrestricted
0 = Supervisor access
1 = User access
IARB — Interrupt Arbitration
Each module that generates interrupts must have an IARB value. IARB values are
used to arbitrate between interrupt requests of the same priority.
D.4.2 QTEST — QSM Test Register
$YFFC02
D
Used for factory test only.
D.4.3 QILR — QSM Interrupt Level Register
QIVR — QSM Interrupt Vector Register
$YFFC04
$YFFC05
15
0
14
0
13
11
10
8
7
0
0
ILQSPI
0
ILSCI
0
INTV
RESET:
0
0
0
0
0
0
0
0
0
1
1
1
1
The values of the ILQSPI and ILSCI fields in QILR determine the priority of QSPI and
SCI interrupt requests. QIVR determines the value of the interrupt vector number the
QSM supplies when it responds to an interrupt acknowledge cycle. At reset, QIVR is
initialized to vector number $0F, the uninitialized interrupt vector number. To use in-
terrupt-driven serial communication, a user-defined vector number must be written to
QIVR.
ILQSPI — Interrupt Level for QSPI
When an interrupt request is made, ILQSPI value determines which of the interrupt re-
quest signals is asserted; when a request is acknowledged, the QSM compares this
value to a mask value supplied by the CPU32 to determine whether to respond. ILQS-
PI must have a value in the range $0 (lowest priority) to $7 (highest priority).
ILSCI — Interrupt Level for SCI
When an interrupt request is made, ILSCI value determines which of the interrupt re-
quest signals is asserted. When a request is acknowledged, the QSM compares this
value to a mask value supplied by the CPU32 to determine whether to respond. The
field must have a value in the range $0 (lowest priority) to $7 (highest priority).
If ILQSPI and ILSCI have the same nonzero value, and both submodules simulta-
neously request interrupt service, the QSPI has priority.
MOTOROLA
D-26
REGISTER SUMMARY
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
