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MC68331CFC16 参数 Datasheet PDF下载

MC68331CFC16图片预览
型号: MC68331CFC16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
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D.4 Queued Serial Module  
Table D-13 displays the QSM address map. The column labeled “Access” indicates  
the privilege level at which the CPU must be operating to access the register. A des-  
ignation of “S” indicates that supervisor access is required: a designation of “S/U” in-  
dicates that the register can be programmed to the desired privilege level.  
Table D-13 QSM Address Map  
Access  
S
Address  
$YFFC00  
$YFFC02  
$YFFC04  
$YFFC06  
$YFFC08  
$YFFC0A  
$YFFC0C  
$YFFC0E  
$YFFC10  
$YFFC12  
$YFFC14  
$YFFC16  
$YFFC18  
$YFFC1A  
$YFFC1C  
$YFFC1E  
15  
8 7  
0
QSM MODULE CONFIGURATION (QSMCR)  
QSM TEST (QTEST)  
S
S
QSM INTERRUPT LEVEL (QILR)  
QSM INTERRUPT VECTOR (QIVR)  
S/U  
S/U  
S/U  
S/U  
S/U  
S/U  
S/U  
S/U  
S/U  
S/U  
S/U  
S/U  
S/U  
S/U  
NOT USED  
SCI CONTROL 0 (SCCR0)  
SCI CONTROL 1 (SCCR1)  
SCI STATUS (SCSR)  
SCI DATA (SCDR)  
NOT USED  
NOT USED  
NOT USED  
PQS PIN ASSIGNMENT (PQSPAR)  
PQS DATA (PORTQS)  
D
PQS DATA DIRECTION (DDRQS)  
SPI CONTROL 0 (SPCR0)  
SPI CONTROL 1 (SPCR1)  
SPI CONTROL 2 (SPCR2)  
SPI CONTROL 3 (SPCR3)  
SPI STATUS (SPSR)  
$YFFC20–  
$YFFCFF  
NOT USED  
S/U  
QUEUE RAM  
$YFFD00–  
$YFFD1F  
RECEIVE RAM (RR[0:F])  
TRANSMIT RAM (TR[0:F])  
COMMAND RAM (CR[0:F])  
S/U  
QUEUE RAM  
$YFFD20–  
$YFFD3F  
S/U  
QUEUE RAM  
$YFFD40–  
$YFFD4F  
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.  
D.4.1 QSMCR — QSM Configuration Register  
$YFFC00  
15  
14  
13  
12  
0
11  
0
10  
0
9
0
8
0
7
6
0
5
0
4
0
3
0
0
STOP  
FRZ1  
FRZ0  
SUPV  
IARB  
RESET:  
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
QSMCR bits enable stop and freeze modes, and determine the arbitration priority of  
QSM interrupt requests.  
STOP — Stop Enable  
0 = Normal QSM clock operation  
1 = QSM clock operation stopped  
When STOP is set, the QSM enters low-power stop mode. System clock input to the  
module is disabled. While STOP is asserted, only QSMCR reads are guaranteed to be  
MC68331  
REGISTER SUMMARY  
MOTOROLA  
D-25  
USER’S MANUAL