Table A-6 16.78 MHz AC Timing
(V and V
= 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
DDSYN
SS
A
L
H
Num
F1
1
Characteristic
Frequency of Operation (32.768 kHz crystal)
Clock Period
Symbol
Min
0.13
59.6
476
59.6
24
Max
16.78
—
Unit
MHz
ns
2
f
t
cyc
1A
1B
ECLK Period
t
t
—
ns
Ecyc
Xcyc
3
External Clock Input Period
—
ns
2, 3 Clock Pulse Width
t
—
ns
CW
2A, 3A ECLK Pulse Width
t
236
29.8
—
—
ns
ECW
3
2B, 3B External Clock Input High/Low Time
4, 5 Clock Rise and Fall Time
t
—
ns
XCHL
t
5
ns
Crf
4A, 5A Rise and Fall Time — All Outputs except CLKOUT
t
—
8
ns
rf
4
4B, 5B External Clock Rise and Fall Time
t
—
5
ns
XCrf
6
7
Clock High to Address, FC, SIZE, RMC Valid
t
0
29
59
—
ns
CHAV
Clock High to Address, Data, FC, SIZE, RMC High Impedance
Clock High to Address, FC, SIZE, RMC Invalid
Clock Low to AS, DS, CS Asserted
t
0
ns
CHAZx
8
t
0
ns
CHAZn
9
t
t
2
25
15
22
—
ns
CLSA
5
9A
9C
11
AS to DS or CS Asserted (Read)
–15
2
ns
STSA
Clock Low to IFETCH, IPIPE Asserted
t
ns
CLIA
A
Address, FC, SIZE, RMC Valid
to AS, CS Asserted
t
15
ns
AVSA
12
Clock Low to AS, DS, CS Negated
t
2
2
29
22
—
ns
ns
ns
CLSN
12A Clock Low to IFETCH, IPIPE Negated
t
CLIN
SNAI
13
AS, DS, CS Negated to
t
15
Address, FC, SIZE Invalid (Address Hold)
14
AS, CS Width Asserted
t
100
45
40
40
—
15
0
—
—
—
—
59
—
29
29
—
—
29
—
—
—
—
—
80
—
55
—
90
50
29
—
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SWA
14A DS, CS Width Asserted (Write)
t
SWAW
t
SWDW
14B AS, CS Width Asserted (Fast Write Cycle)
6
15
16
17
18
20
21
22
23
24
25
26
27
AS, DS, CS Width Negated
t
SN
Clock High to AS, DS, R/W High Impedance
AS, DS, CS Negated to R/W Negated
Clock High to R/W High
t
CHSZ
SNRN
CHRH
t
t
Clock High to R/W Low
t
t
t
0
CHRL
RAAA
RASA
R/W Asserted to AS, CS Asserted
R/W Low to DS, CS Asserted (Write)
Clock High to Data Out Valid
15
70
—
15
15
15
5
t
CHDO
Data Out Valid to Negating Edge of AS, CS
DS, CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS, CS Asserted (Write)
Data In Valid to Clock Low (Data Setup)
t
DVASN
t
SNDOI
t
DVSA
t
DICL
27A Late BERR, HALT Asserted to Clock Low (Setup Time)
t
20
0
BELCL
28
29
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
t
SNDN
7
DS, CS Negated to Data In Invalid (Data In Hold)
t
0
SNDI
SHDI
7, 8
29A DS, CS Negated to Data In High Impedance
t
—
15
—
—
—
1
7
30
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
t
CLDI
7
30A CLKOUT Low to Data In High Impedance
t
CLDH
9
31
33
35
37
DSACK[1:0] Asserted to Data In Valid
Clock Low to BG Asserted/Negated
BR Asserted to BG Asserted (RMC Not Asserted)
BGACK Asserted to BG Negated
t
DADI
t
CLBAN
10
t
t
t
BRAGA
cyc
cyc
t
1
GAGN
MOTOROLA
A-8
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
