Table A-6 16.78 MHz AC Timing, (Continued)
(V and V
= 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
DDSYN
SS
A
L
H
Num
Characteristic
Symbol
Min
2
Max
—
Unit
39
BG Width Negated
t
t
t
GH
cyc
39A BG Width Asserted
46 R/W Width Asserted (Write or Read)
t
1
—
GA
cyc
t
150
90
5
—
ns
ns
ns
RWA
46A R/W Width Asserted (Fast Write or Read Cycle)
t
—
RWAS
47A Asynchronous Input Setup Time
t
—
AIST
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
47B Asynchronous Input Hold Time
t
15
—
0
—
30
—
28
—
—
—
29
—
—
—
—
—
—
—
10
ns
ns
ns
ns
ns
AIHT
11
48
53
54
55
56
57
70
71
72
73
74
75
76
77
78
DSACK[1:0] Asserted to BERR, HALT Asserted
Data Out Hold from Clock High
t
DABA
DOCH
t
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
RESET Pulse Width (Reset Instruction)
BERR Negated to HALT Negated (Rerun)
Clock Low to Data Bus Driven (Show)
Data Setup Time to Clock Low (Show)
Data Hold from Clock Low (Show)
BKPT Input Setup Time
t
—
40
512
0
CHDH
t
RADC
t
t
cyc
HRPW
t
ns
BNHN
t
0
ns
ns
ns
ns
ns
SCLDD
t
15
10
15
10
20
0
SCLDS
t
SCLDH
t
BKST
A
BKPT Input Hold Time
t
BKHT
Mode Select Setup Time
t
t
cyc
MSS
Mode Select Hold Time
t
ns
MSH
12
RESET Assertion Time
t
4
t
RSTA
RSTR
cyc
cyc
13
RESET Rise Time
t
—
t
Table A-6a 20.97 MHz AC Timing
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T )
DD
DDSYN
SS
A
L
H
Num
F1
1
Characteristic
Frequency of Operation (32.768 kHz crystal)
Clock Period
Symbol
Min
0.13
47.7
381
47.7
18.8
183
23.8
—
Max
20.97
—
Unit
MHz
ns
2
f
t
cyc
1A
1B
ECLK Period
t
t
—
ns
Ecyc
3
External Clock Input Period
—
ns
Xcyc
2, 3 Clock Pulse Width
t
—
ns
CW
2A, 3A ECLK Pulse Width
t
—
ns
ECW
3
2B, 3B External Clock Input High/Low Time
4, 5 Clock Rise and Fall Time
t
—
ns
XCHL
t
5
ns
Crf
4A, 5A Rise and Fall Time — All Outputs except CLKOUT
t
—
8
ns
rf
4
4B, 5B External Clock Rise and Fall Time
t
—
5
ns
XCrf
6
7
Clock High to Address, FC, SIZE, RMC Valid
t
0
23
47
—
ns
CHAV
Clock High to Address, Data, FC, SIZE, RMC High Impedance
Clock High to Address, FC, SIZE, RMC Invalid
Clock Low to AS, DS, CS Asserted
t
0
ns
CHAZx
8
t
0
ns
CHAZn
9
t
t
0
23
10
22
—
ns
CLSA
5
9A
9C
11
AS to DS or CS Asserted (Read)
–10
2
ns
STSA
Clock Low to IFETCH, IPIPE Asserted
t
ns
CLIA
Address, FC, SIZE, RMC Valid
to AS, CS Asserted
t
10
ns
AVSA
12
Clock Low to AS, DS, CS Negated
t
2
2
23
22
—
ns
ns
ns
CLSN
12A Clock Low to IFETCH, IPIPE Negated
t
CLIN
13
AS, DS, CS Negated to
t
10
SNAI
Address, FC, SIZE Invalid (Address Hold)
MC68331
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-9
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
