Table A-6a 20.97 MHz AC Timing, (Continued)
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T )
DD
DDSYN
SS
A
L
H
Num
Characteristic
Symbol
Min
80
36
32
32
—
10
0
Max
—
—
—
—
47
—
23
23
—
—
23
—
—
—
—
—
60
—
48
—
72
46
23
—
2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
AS, CS Width Asserted
t
SWA
14A DS, CS Width Asserted (Write)
t
SWAW
t
SWDW
14B AS, CS Width Asserted (Fast Write Cycle)
6
15
16
17
18
20
21
22
23
24
25
26
27
AS, DS, CS Width Negated
t
SN
Clock High to AS, DS, R/W High Impedance
AS, DS, CS Negated to R/W Negated
Clock High to R/W High
t
CHSZ
SNRN
CHRH
t
t
Clock High to R/W Low
t
t
t
0
CHRL
RAAA
RASA
R/W Asserted to AS, CS Asserted
R/W Low to DS, CS Asserted (Write)
Clock High to Data Out Valid
10
54
—
10
10
10
5
t
CHDO
Data Out Valid to Negating Edge of AS, CS
DS, CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS, CS Asserted (Write)
Data In Valid to Clock Low (Data Setup)
t
DVASN
t
SNDOI
t
DVSA
t
DICL
27A Late BERR, HALT Asserted to Clock Low (Setup Time)
t
15
0
BELCL
28
29
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
t
SNDN
A
7
DS, CS Negated to Data In Invalid (Data In Hold)
t
0
SNDI
SHDI
7, 8
29A DS, CS Negated to Data In High Impedance
t
—
10
—
—
—
1
7
30
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
t
CLDI
7
30A CLKOUT Low to Data In High Impedance
t
CLDH
9
31
33
35
37
39
DSACK[1:0] Asserted to Data In Valid
Clock Low to BG Asserted/Negated
BR Asserted to BG Asserted (RMC Not Asserted)
BGACK Asserted to BG Negated
BG Width Negated
t
DADI
t
CLBAN
10
t
t
t
t
t
BRAGA
cyc
cyc
cyc
cyc
t
1
GAGN
t
2
—
—
—
—
—
GH
39A BG Width Asserted
t
1
GA
46
R/W Width Asserted (Write or Read)
t
115
70
5
ns
ns
ns
RWA
46A R/W Width Asserted (Fast Write or Read Cycle)
47A Asynchronous Input Setup Time
t
RWAS
t
AIST
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
47B Asynchronous Input Hold Time
t
12
—
0
—
30
—
23
—
—
—
23
—
—
—
—
—
—
—
10
ns
ns
ns
ns
ns
AIHT
11
48
53
54
55
56
57
70
71
72
73
74
75
76
77
78
DSACK[1:0] Asserted to BERR, HALT Asserted
Data Out Hold from Clock High
t
DABA
t
DOCH
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
RESET Pulse Width (Reset Instruction)
BERR Negated to HALT Negated (Rerun)
Clock Low to Data Bus Driven (Show)
Data Setup Time to Clock Low (Show)
Data Hold from Clock Low (Show)
BKPT Input Setup Time
t
—
32
512
0
CHDH
t
RADC
t
t
cyc
HRPW
t
ns
BNHN
t
0
ns
ns
ns
ns
ns
SCLDD
t
10
10
10
10
20
0
SCLDS
t
SCLDH
t
BKST
BKPT Input Hold Time
t
BKHT
Mode Select Setup Time
t
t
cyc
MSS
Mode Select Hold Time
t
ns
MSH
12
RESET Assertion Time
t
4
t
RSTA
RSTR
cyc
cyc
13,14
RESET Rise Time
t
—
t
MOTOROLA
A-10
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
