Table A-4a 20.97 MHz Clock Control Timing
(V and V
= 5.0 Vdc ±5%, V = 0 Vdc, T = T to T
32.768 kHz reference)
DD
DDSYN
SS
A
L
H,
Num
Characteristic
Symbol
Min
25
Max
50
Unit
1
2
PLL Reference Frequency Range
f
kHz
ref
1
System Frequency
dc
20.97
20.97
20.97
20
On-Chip PLL System Frequency
External Clock Operation
f
0.131
dc
MHz
sys
2,3,4,5
3
4
5
PLL Lock Time
t
—
ms
lpll
6
VCO Frequency
f
—
2 (f max)
MHz
MHz
VCO
sys
Limp Mode Clock Frequency
SYNCR X bit = 0
f
limp
—
—
f
max/2
sys
SYNCR X bit = 1
f
max
sys
2,3,4,7
6
CLKOUT Stability
C
%
stab
Short term (5 µs interval)
Long term (500 µs interval)
–0.5
–0.05
0.5
0.05
Notes for Tables A–4 and A–4a
1. All internal registers retain data at 0 Hz
2 This parameter is periodically sampled rather than 100% tested.
A
3. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total
external resistance from the XFC pin due to external leakage must be greater than 15 M ∫ to guarantee this
specification. Filter network geometry can vary depending upon operating environment (See 4.3 System
Clock).
4. Proper layout procedures must be followed to achieve specifications.
5. Assumes that stable V
is applied, and that the crystal oscillator is stable. Lock time is measured from
DDSYN
the time V and V
are valid until RESET is released. This specification also applies to the period
DD
DDSYN
required for PLL lock after changing the W and Y frequency control bits in the synthesizer control register
(SYNCR) while the PLL is running, and to the period required for the clock to lock after LPSTOP.
6. Internal VCO frequency (f
) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a
VCO
divide-by-two circuit that is not in the synthesizer feedback loop. When X = 0, the divider is enabled, and f
sys
= f
÷ 4. When X = 1, the divider is disabled, and f
= f
÷ 2. X must equal one when operating at
VCO
sys
VCO
maximum specified f
.
sys
7. Stability is the average deviation from the programmed frequency measured over the specified interval at
maximum f . Measurements are made with the device powered by filtered supplies and clocked by a sta-
sys
ble external clock signal. Noise injected into the PLL circuitry via V
and V and variation in crystal
DDSYN
SS
oscillator frequency increase the C
percentage for a given interval. When clock stability is a critical con-
stab
straint on control system operation, this parameter should be measured during functional testing of the final
system.
MOTOROLA
A-4
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
