10
INTERRUPT
REQUESTS
11
TMSK2
TFLG2
EDGE
DETECT
LOGIC
SYNCHRONIZER
&
DIGITAL FILTER
OVERFLOW
ENABLE
PAI
2:1
MUX
PACNT
8-BIT COUNTER
7
PACTL
INTERNAL
DATA BUS
PCLK
TCNT OVERFLOW
CAPTURE/COMPARE CLK
MUX
PRESCALER ÷ 512
16/32 PLS ACC BLOCK
Figure 7-5 Pulse Accumulator Block Diagram
7.11 Pulse-Width Modulation Unit
The pulse-width modulation (PWM) unit has two output channels, PWMA and PWMB.
A single clock output from the prescaler multiplexer drives a 16-bit counter that is used
to control both channels. Figure 7-6 is a block diagram of the pulse-width modulation
unit.
The PWM unit has two operational modes. Fast mode uses a clocking rate equal to 1/
256 of the prescaler output rate; slow mode uses a rate equal to 1/32768 of the pres-
caler output rate. The duty cycle ratios of the two PWM channels can be individually
controlled by software. The PWMA pin can also output the clock that drives the PWM
counter. PWM pins can also be used as output pins.
MC68331
GENERAL-PURPOSE TIMER
MOTOROLA
7-15
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
